ICCAD 1999: San Jose, California, USA

• Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
  Marsh: min-area retiming with setup and hold constraints. 2-6
  
• Robert M. Fuhrer, Steven M. Nowick:
  OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic. 7-13
  
• Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
  Bit-level arithmetic optimization for carry-save additions. 14-19
  
• Hussein Etawil, Shawki Areibi, Anthony Vannelli:
  Attractor-repeller approach for global placement. 20-24
  
• Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz:
  Cell replication and redundancy elimination during placement for cycle time optimization. 25-30
  
• Jinan Lou, Wei Chen, Massoud Pedram:
  Concurrent logic restructuring and placement for timing closure. 31-36
  
• Aiguo Xie, Peter A. Beerel:
  Implicit enumeration of strongly connected components. 37-40
  
• In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi:
  Least fixpoint approximations for reachability analysis. 41-44
  
• Hiroyuki Higuchi, Fabio Somenzi:
  Lazy group sifting for efficient symbolic state traversal of FSMs. 45-49
  
• Wolfgang Günther, Rolf Drechsler:
  Efficient manipulation algorithms for linearly transformed BDDs. 50-54
  
• Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli:
  Noise analysis of non-autonomous radio frequency circuits. 55-60
  
• Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov:
  New methods for speeding up computation of Newton updates in harmonic balance. 61-64
  
• Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee:
  Design and optimization of LC oscillators. 65-69
  
• Alper Demir, Peter Feldmann:
  Modeling and simulation of the interference due to digital switching in mixed-signal ICs. 70-75
  
• Chunhong Chen, Majid Sarrafzadeh:
  Provably good algorithm for low power consumption with dual supply voltages. 76-79
  
• Khurram Muhammad, Kaushik Roy:
  A novel design methodology for high performance and low power digital filters. 80-83
  
• Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang:
  A bipartition-codec architecture to reduce power in pipelined circuits. 84-90
  
• Tatjana Serdar, Carl Sechen:
  AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. 91-97
  
• Serkan Askar, Maciej J. Ciesielski:
  Analytical approach to custom datapath design. 98-101
  
• Yanbin Jiang, Sachin S. Sapatnekar:
  An integrated algorithm for combined placement and libraryless technology mapping. 102-106
  
• Min Zhao, Sachin S. Sapatnekar:
  Timing-driven partitioning for two-phase domino and mixed static/domino implementations. 107-110
  
• Ki-Wook Kim, C. L. Liu, Sung-Mo Kang:
  Implication graph based domino logic synthesis. 111-114
  
• Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu:
  Synthesis for multiple input wires replacement of a gate for wiring consideration. 115-119
  
• Tuyen V. Nguyen, Peter O'Brien, David W. Winston:
  Transient sensitivity computation for transistor level analysis and tuning. 120-123
  
• Yi-Kan Cheng, Sung-Mo Kang:
  An efficient method for hot-spot identification in ULSI circuits. 124-127
  
• Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
  A scalable substrate noise coupling model for mixed-signal ICs. 128-131
  
• Pinhong Chen, Kurt Keutzer:
  Towards true crosstalk noise analysis. 132-138
  
• Paul Tafertshofer, Andreas Ganz:
  SAT based ATPG using fast justification and propagation in the implication graph. 139-146
  
• Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
  Techniques for improving the efficiency of sequential circuit test generation. 147-151
  
• Fatih Kocan, Daniel G. Saab:
  Concurrent D-algorithm on reconfigurable hardware. 152-156
  
• Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley:
  A new heuristic for rectilinear Steiner trees. 157-162
  
• Jason Cong, Jie Fang, Kei-Yong Khoo:
  An implicit connection graph maze routing algorithm for ECO routing. 163-167
  
• Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky:
  The associative-skew clock routing problem. 168-172
  
• Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger:
  Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. 173-177
  
• David S. Kung, Ruchir Puri:
  Optimal P/N width ratio selection for standard cell libraries. 178-184
  
• Rajeev Murgai:
  Performance optimization under rise and fall parameters. 185-190
  
• Yutaka Tamiya:
  Performance optimization using separator sets. 191-194
  
• Martin Charles Golumbic, Aviad Mintz:
  Factoring logic functions using graph partitioning. 195-199
  
• Bernard N. Sheehan:
  TICER: realizable reduction of extracted RC circuits. 200-203
  
• Anirudh Devgan, Peter R. O'Brien:
  Realizable reduction for RC interconnect circuits. 204-207
  
• Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng:
  RLC interconnect delay estimation via moments of amplitude and phase response. 208-213
  
• Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
  Practical considerations for passive reduction of RLC circuits. 214-220
  
• Ellen Sentovich, David L. Dill, Serdar Tasiran:
  Formal verification meets simulation (tutorial abstract). 221
  
• Mattan Kamon, Steve McCormick, Ken Sheperd:
  Interconnect parasitic extraction in the digital IC design methodology. 223-231
  
• Christoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen:
  Cycle time and slack optimization for VLSI-chips. 232-238
  
• Ivan S. Kourtev, Eby G. Friedman:
  Clock skew scheduling for improved reliability via quadratic programming. 239-243
  
• Chandramouli Visweswariah, Andrew R. Conn:
  Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. 244-252
  
• Rainer Leupers, Peter Marwedel:
  Function inlining under code size constraints for embedded processors. 253-256
  
• Daniel Benyamin, William H. Mangione-Smith:
  Function unit specialization through code analysis. 257-260
  
• Margarida F. Jacome, Gustavo de Veciana:
  Lower bound on latency for VLIW ASIP datapaths. 261-269
  
• Tony Givargis, Jörg Henkel, Frank Vahid:
  Interface and cache power exploration for core-based embedded system design. 270-273
  
• Eui-Young Chung, Luca Benini, Giovanni De Micheli:
  Dynamic power management using adaptive learning tree. 274-279
  
• Giuseppe Bernacchia, Marios C. Papaefthymiou:
  Analytical macromodeling for high-level power estimation. 280-283
  
• Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino:
  Parameterized RTL power models for combinational soft macros. 284-288
  
• Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
  Validation and test generation for oscillatory noise in VLSI interconnects. 289-296
  
• Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao:
  Fault modeling and simulation for crosstalk in system-on-chip interconnects. 297-303
  
• Alfred V. Gomes, Abhijit Chatterjee:
  Robust optimization based backtrace method for analog circuits. 304-308
  
• Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
  A methodology for correct-by-construction latency insensitive design. 309-315
  
• Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev:
  What is the cost of delay insensitivity? 316-323
  
• Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens:
  Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. 324-331
  
• Sung Tae Jung, Chris J. Myers:
  Direct synthesis of timed asynchronous circuits. 332-338
  
• David L. Rhodes, Wayne Wolf:
  Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication. 339-342
  
• Gang Qu, Miodrag Potkonjak:
  Power minimization using system-level partitioning of applications with quality of service requirements. 343-346
  
• Felice Balarin:
  Worst-case analysis of discrete systems. 347-353
  
• Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani:
  Integrated floorplanning and interconnect planning. 354-357
  
• Jason Cong, Tianming Kong, David Zhigang Pan:
  Buffer block planning for interconnect-driven floorplanning. 358-363
  
• Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang:
  A clustering- and probability-based approach for time-multiplexed FPGA partitioning. 364-369
  
• Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu:
  The Chebyshev expansion based passive model for distributed interconnect networks. 370-375
  
• Emad Gad, Michel S. Nakhla:
  Model reduction for DC solution of large nonlinear circuits. 376-379
  
• Jing-Rebecca Li, Jacob White:
  Efficient model reduction of interconnect via approximate system gramians. 380-384
  
• Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
  A framework for testing core-based systems-on-a-chip. 385-390
  
• Krishnendu Chakrabarty:
  Test scheduling for core-based systems. 391-394
  
• Qiushuang Zhang, Ian G. Harris:
  Partial BIST insertion to eliminate data correlation. 395-399
  
• Huiqun Liu, D. F. Wong:
  A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. 400-405
  
• Inki Hong, Miodrag Potkonjak, Lisa M. Guerra:
  Throughput optimization of general non-linear computations. 406-409
  
• Junhyung Um, Taewhan Kim, C. L. Liu:
  Optimal allocation of carry-save-adders in arithmetic optimization. 410-413
  
• Soha Hassoun, Carolyn McCreary:
  Regularity extraction via clan-based structural circuit decomposition. 414-419
  
• Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
  Repeater insertion in tree structured inductive interconnect. 420-424
  
• Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz:
  Interconnect scaling implications for CAD. 425-429
  
• Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
  Is wire tapering worthwhile? 430-436
  
• Michael W. Beattie, Lawrence T. Pileggi:
  Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. 437-444
  
• A. J. Dammers, N. P. van der Meijs:
  Virtual screening: a step towards a sparse partial inductance matrix. 445-452
  
• Junfeng Wang, Johannes Tausch, Jacob K. White:
  A wide frequency range surface integral formulation for 3-D RLC extraction. 453-458
  
• Sani R. Nassif, Tuyen V. Nguyen:
  SOI technology and tools (abstract). 459
  
• Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar:
  System level design and debug of high-performance embedded media systems (tutorial). 461
  
• Irith Pomeranz, Sudhakar M. Reddy:
  An approach for improving the levels of compaction achieved by vector omission. 463-466
  
• Bapiraju Vinnakota:
  Deep submicron defect detection with the energy consumption ratio. 467-470
  
• Pankaj Pant, Abhijit Chatterjee:
  Efficient diagnosis of path delay faults in digital logic circuits. 471-476
  
• Preeti Ranjan Panda:
  Memory bank customization and assignment in behavioral synthesis. 477-481
  
• Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
  Memory binding for performance optimization of control-flow intensive behaviors. 482-488
  
• Dirk Herrmann, Rolf Ernst:
  Improved interconnect sharing by identity operation insertion. 489-493
  
• Thomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani:
  Formal specification and verification of a dataflow processor array. 494-499
  
• Dragos Lungeanu, C.-J. Richard Shi:
  Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. 500-504
  
• Harry Hsieh, Felice Balarin:
  Synchronous equivalence for embedded systems: a tool for design exploration. 505-510
  
• Rajeev Murgai:
  On the global fanout optimization problem. 511-515
  
• Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj:
  LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay. 516-519
  
• Jie-Hong Roland Jiang, Iris Hui-Ru Jiang:
  Optimum loading dispersion for high-speed tree-type decision circuitry. 520-525
  
• Clayton B. McDonald, Randal E. Bryant:
  Symbolic functional and timing verification of transistor-level circuits. 526-530
  
• Kenneth L. Shepard, Dae-Jin Kim:
  Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis. 531-538
  
• Alexander Saldanha:
  Functional timing optimization. 539-543
  
• Yuji Kukimoto, Robert K. Brayton:
  Timing-safe false path removal for combinational modules. 544-550
  
• Rachid Helaihel, Kunle Olukotun:
  JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations. 551-557
  
• Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
  FunState - an internal design representation for codesign. 558-565
  
• Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
  Fast performance analysis of bus-based system-on-chip communication architectures. 566-573
  
• Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton:
  Probabilistic state space search. 574-579
  
• Jules P. Bergmann, Mark Horowitz:
  Improving coverage analysis and test generation for large designs. 580-583
  
• Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
  Modeling design constraints and biasing in simulation using BDDs. 584-590
  
• Edoardo Charbon, Ilhami Torunoglu:
  Copyright protection of designs based on multi source IPs. 591-595
  
• Darko Kirovski, Miodrag Potkonjak:
  Localized watermarking: methodology and application to operation scheduling. 596-599
  
• Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong:
  Copy detection for intellectual property protection of VLSI designs. 600-605
  
• Jacob White, Gary K. Fedder, Tamal Mukherjee:
  Path toward future CAD environments for MEMS (tutorial abstract). 606
  
• Nikil D. Dutt, Eric M. Foster:
  Design of a set-top box system on a chip (abstract). 608
  
• Nikil D. Dutt, Brian Kelley:
  On the rapid prototyping and design of a wireless communication system on a chip (abstract). 609
  
• Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong:
  Advances in transistor timing, simulation, and optimization (tutorial abstract). 611
  
• Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich:
  Embedded Java: techniques and applications (tutorial abstract). 613
  

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