ICCAD 2005:
San Jose, California, USA
2005 International Conference on Computer-Aided Design (ICCAD'05), November 6-10, 2005, San Jose, CA, USA.
IEEE Computer Society 2005, ISBN 0-7803-9254-X 
- Wenrui Gong, Gang Wang, Ryan Kastner:
Storage assignment during high-level synthesis for configurable architectures.
3-6
- Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida:
Performance-driven read-after-write dependencies softening in high-level synthesis.
7-12
- Paulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa:
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications.
13-16
- Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He:
FPGA device and architecture evaluation considering process variations.
19-24
- Yajun Ran, Malgorzata Marek-Sadowska:
Via-configurable routing architectures and fast design mappability estimation for regular fabrics.
25-32
- Kwok-Shing Leung:
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill.
33-38
- Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan:
Computational geometry based placement migration.
41-47
- Min Pan, Natarajan Viswanathan, Chris C. N. Chu:
An efficient and effective detailed placement algorithm.
48-55
- Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.
56-63
- Xin Hao, Forrest Brewer:
Wirelength optimization by optimal block orientation.
64-70
- Erkan Acar, Sule Ozev:
Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions.
73-79
- Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng:
Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
80-87
- Anuja Sehgal, Krishnendu Chakrabarty:
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.
88-93
- Krishnendu Chakrabarty, J. E. Chen:
A cocktail approach on random access scan toward low power and high efficiency test.
94-99
- David Bordoley, Hieu Nguyen, Mani Soma:
A statistical study of the effectiveness of BIST jitter measurement techniques.
100-107
- Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor.
111-117
- Richard McGowen:
Adaptive designs for power and thermal optimization.
118-121
- Robert B. Staszewski, Khurram Muhammad, Dirk Leipold:
Digital RF processor (DRP/spl trade/) for cellular phones.
122-129
- Jianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa:
A layout dependent full-chip copper electroplating topography model.
133-140
- James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning:
Interval-valued statistical modeling of oxide chemical-mechanical polishing.
141-148
- Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu:
Fast and efficient phase conflict detection and correction in standard-cell layouts.
149-156
- Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.
159-164
- Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Robust mixed-size placement under tight white-space constraints.
165-172
- Andrew B. Kahng, Sherief Reda:
Intrinsic shortest path length: a new, accurate a priori wirelength estimator.
173-180
- Yinghua Li, Alex Kondratyev, Robert K. Brayton:
Synthesis methodology for built-in at-speed testing.
183-188
- Chuan Lin, Jia Wang, Hai Zhou:
Clustering for processing rate optimization.
189-195
- Sanghamitra Roy, Weijen Chen:
ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing.
196-203
- Tsu-Jae King:
FinFETs for nanoscale CMOS digital integrated circuits.
207-210
- Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen:
Physics-based compact modeling for nonclassical CMOS.
211-216
- Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications.
217-224
- Jeremy A. Rowlette, Eric Pop, Sanjiv Sinha, Mathew Panzer, Kenneth E. Goodson:
Thermal simulation techniques for nanoscale transistors.
225-228
- Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
An automated technique for topology and route generation of application specific on-chip interconnection networks.
231-237
- Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner:
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip.
238-245
- Ümit Y. Ogras, Radu Marculescu:
Application-specific network-on-chip architecture customization via long-range link insertion.
246-253
- Jeremy Chan, Sri Parameswaran:
NoCEE: energy macro-model extraction methodology for network on chip routers.
254-259
- Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors.
263-270
- Guilin Chen, Mahmut T. Kandemir:
Code restructuring for improving cache performance of MPSoCs.
271-274
- Mahmut T. Kandemir:
2D data locality: definition, abstraction, and application.
275-278
- Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu:
Integrating loop and data optimizations for locality within a constraint network based framework.
279-282
- Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch:
System level verification of digital signal processing applications based on the polynomial abstraction technique.
285-290
- Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan:
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra.
291-296
- Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
RTL SAT simplification by Boolean and interval arithmetic reasoning.
297-302
- Guilin Chen, Mahmut T. Kandemir:
Runtime integrity checking for inter-object connections.
303-306
- Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang:
Post-placement voltage island generation under performance requirement.
309-316
- Liang Deng, Martin D. F. Wong:
Buffer insertion under process variations for delay minimization.
317-321
- Ruiming Chen, Hai Zhou:
Efficient algorithms for buffer insertion in general circuits based on network flow.
322-326
- Chuan Lin, Hai Zhou:
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.
329-334
- Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck Chang:
Flip-flop insertion with shifted-phase clocks for FPGA power reduction.
335-342
- Amit Gupta, Charles Selvidge:
Acyclic modeling of combinational loops.
343-347
- Yu Zhong, Martin D. F. Wong:
Fast algorithms for IR drop analysis in large power grid.
351-357
- Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm:
Incremental partitioning-based vectorless power grid verification.
358-364
- Sanjay Pant, David Blaauw:
Static timing analysis considering power supply variations.
365-371
- André DeHon, Konstantin Likharev:
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation.
375-382
- Navin Srivastava, Kaustav Banerjee:
Performance analysis of carbon nanotube interconnects for VLSI applications.
383-390
- Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra:
DiCER: distributed and cost-effective redundancy for variation tolerance.
393-397
- Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
398-405
- Suwen Yang, Mark R. Greenstreet:
Noise margin analysis for dynamic logic circuits.
406-412
- Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli:
Efficient analog platform characterization through analog constraint graphs.
415-421
- Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang:
Performance-centering optimization for system-level analog design exploration.
422-429
- Anuradha Agarwal, Ranga Vemuri:
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.
430-436
- Ravishankar Rao, Sarma B. K. Vrudhula:
Battery optimization vs energy optimization: which to choose and when?
439-445
- Bren Mochocki, Razvan Racu, Rolf Ernst:
Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems.
446-449
- Jaewon Seo, Taewhan Kim, Nikil D. Dutt:
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
450-455
- Feihui Li, Guilin Chen, Mahmut T. Kandemir:
Compiler-directed voltage scaling on communication links for reducing power consumption.
456-460
- Tamal Mukherjee:
Design automation issues for biofluidic microchips.
463-470
- Paul W. K. Rothemund:
Design of DNA origami.
471-478
- Elena Dubrova, Maxim Teslenko, Andrés Martinelli:
Kauffman networks: analysis and applications.
479-484
- Bradley N. Bond, Luca Daniel:
Parameterized model order reduction of nonlinear dynamical systems.
487-494
- Bo Hu, C.-J. Richard Shi:
Fast-yet-accurate PVT simulation by combined direct and iterative methods.
495-501
- Arthur Nieuwoudt, Yehia Massoud:
Robust automated synthesis methodology for integrated spiral inductors with variability.
502-507
- Ashish Kumar Singh, Murari Mani, Michael Orshansky:
Statistical technology mapping for parametric yield.
511-518
- Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing structural bias in technology mapping.
519-526
- Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths.
527-531
- Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge:
Total power-optimal pipelining and parallel processing under process variations in nanometer technology.
535-540
- Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De:
Serial-link bus: a low-power on-chip bus architecture.
541-546
- Greg Stiff, Frank Vahid:
New decompilation techniques for binary-level co-processor generation.
547-554
- Tamás Roska:
Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays.
557-564
- Amitabh Chaudhary, Danny Z. Chen, Kevin Whitton, Michael T. Niemier, Ramprasad Ravichandran:
Eliminating wire crossings for molecular quantum-dot cellular automata implementation.
565-571
- Jeng-Liang Tsai, Lizheng Zhang:
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis.
575-581
- Minsik Cho, Suhail Ahmed, David Z. Pan:
TACO: temperature aware clock-tree optimization.
582-587
- Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen:
Statistical based link insertion for robust clock network design.
588-591
- Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
592-596
- Ting Mei, Jaijeet S. Roychowdhury:
An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators.
599-603
- Ting Mei, Jaijeet S. Roychowdhury:
Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators.
604-609
- Kapil D. Boianapally, Ting Mei, Jaijeet S. Roychowdhury:
A multi-harmonic probe technique for computing oscillator steady states.
610-613
- Amit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan:
Steady-state analysis of voltage and current controlled oscillators.
618-623
- Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout.
627-634
- Yong Zhan, Sachin S. Sapatnekar:
A high efficiency full-chip thermal simulation algorithm.
635-638
- Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang:
Fast thermal simulation for architecture level dynamic thermal management.
639-644
- Peng Li:
Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality.
645-651
- Seth Copen Goldstein:
The impact of the nanoscale on computing systems.
655-661
- Chris Dwyer:
Computer-aided design for DNA self-assembly: process and applications.
662-667
- Mehdi Baradaran Tahoori:
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.
668-672
- Zhenhai Zhu, Jacob K. White:
FastSies: a fast stochastic integral equation solver for modeling the rough surface effect.
675-682
- Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen:
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis.
683-690
- Mosin Mondal, Yehia Massoud:
Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance.
691-696
- Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark:
Statistical critical path analysis considering correlations.
699-704
- Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov:
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.
705-712
- Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs.
713-718
- Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas:
Projection-based performance modeling for inter/intra-die variations.
721-727
- Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li:
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS).
728-735
- Amit Agarwal, Kunhyuk Kang, Kaushik Roy:
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.
736-741
- Jason Cong, Yan Zhang:
Thermal via planning for 3-D ICs.
745-752
- Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang:
A routing algorithm for flip-chip design.
753-758
- Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
An escape routing framework for dense boards with high-speed design constraints.
759-766
- Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Optimal routing algorithms for pin clusters in high-density multichip modules.
767-774
- Aravind Vijayakumar, Forrest Brewer:
Weighted control scheduling.
777-783
- Daniel L. Rosenband:
Hardware synthesis from guarded atomic actions with performance specifications.
784-791
- Love Singhal, Elaheh Bozorgzadeh:
Fast timing closure by interconnect criticality driven delay relaxation.
792-797
- Ngai Wong, Venkataramanan Balakrishnan:
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration.
801-805
- Xin Li, Peng Li, Lawrence T. Pileggi:
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.
806-812
- Dmitry Vasilyev, Jacob K. White:
A more reliable reduction algorithm for behavioral model extraction.
813-820
- Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He:
An efficient method for terminal reduction of interconnect circuits considering delay variations.
821-826
- Khaled R. Heloue, Farid N. Najm:
Statistical timing analysis with two-sided constraints.
829-836
- Debjit Sinha, Hai Zhou:
A unified framework for statistical timing analysis with coupling and multiple input switching.
837-843
- Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.
844-851
- Panagiotis Manolios, Sudarshan K. Srinivasan:
Verification of executable pipelined machines with bit-level interfaces.
855-862
- Panagiotis Manolios, Sudarshan K. Srinivasan:
A complete compositional reasoning framework for the efficient verification of pipelined machines.
863-870
- Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-verification debugging of hierarchical designs.
871-876
- Roy Armoni, Sergey Egorov, Ranan Fraer, Dmitry Korchemny, Moshe Y. Vardi:
Efficient LTL compilation for SAT-based model checking.
877-884
- Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti:
SAT based solutions for consistency problems in formal property specifications for open systems.
885-888
- Andrew B. Kahng, Sherief Reda, Qinke Wang:
Architecture and details of a high quality, large-scale analytical placer.
891-898
- Kristofer Vorwerk, Andrew A. Kennings:
Mixed-size placement via line search.
899-904
- Haifeng Qian, Sachin S. Sapatnekar:
A hybrid linear equation solver and its application in quadratic placement.
905-909
- Pai H. Chou, Chulsung Park:
Energy-efficient platform designs for real-world wireless sensing applications.
913-920
- Brian Schott, Michael Bajura:
Power-aware microsensor design.
921-924
- Prabal Dutta, David E. Culler:
System software techniques for low-power operation in wireless sensor networks.
925-932
- Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Expanding the frequency range of AWE via time shifting.
935-938
- Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis.
939-946
- Amit Jain, David Blaauw, Vladimir Zolotov:
Accurate delay computation for noisy waveform shapes.
947-953
- Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh:
Pessimism reduction in crosstalk noise aware STA.
954-961
- Alfred Koelbl, Yuan Lu, Anmol Mathur:
Embedded tutorial: formal equivalence checking between system-level models and RTL.
965-971
- M. Frank Chang:
CDMA/FDMA-interconnects for future ULSI communications.
975-978
- K. O. Kenneth, Kihong Kim, Brian A. Floyd, Jesal L. Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Li Gao, Aravind Sugavanam, Jau-Jr Lin, S. Yu, Changhua Cao, M.-H. Hwang, Y.-R. Ding, S.-H. Hwang, H. Wu, N. Zhang, Joe E. Brewer:
The feasibility of on-chip interconnection using antennas.
979-984
- Michael P. Flynn, Joshua Jaeyoung Kang:
Global signaling over lossy transmission lines.
985-992
- Tohru Ishihara, Farzan Fallah:
A cache-defect-aware code placement algorithm for improving the performance of processors.
995-1001
- Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ibrahim Kolcu:
Improving scratch-pad memory reliability through compiler-guided data block duplication.
1002-1005
- Ankur Agiwal, Montek Singh:
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems.
1006-1013
- Montek Singh:
Memory access optimization of dynamic binary translation for reconfigurable architectures.
1014-1020
- Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester:
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
1023-1028
- Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov:
Gate sizing using incremental parameterized statistical timing analysis.
1029-1036
- Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical gate sizing for timing yield optimization.
1037-1041
- Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-based bug trace minimization with BMC-based refinement.
1045-1051
- Ali Alphan Bayazit, Sharad Malik:
Complementary use of runtime validation and model checking.
1052-1059
- Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz:
Scalable compositional minimization via static analysis.
1060-1067
- Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
Transition-by-transition FSM traversal for reachability analysis in bounded model checking.
1068-1075
- Per Bjesse, James H. Kukula:
Automatic generalized phase abstraction for formal verification.
1076-1082
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