San Jose, California, USA Soha Hassoun (Ed.):
2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA.
ACM 2006, ISBN 1-59593-389-1
Parasitic simulation and modeling
Post-placement optimization techniques
- Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw:
A statistical framework for post-silicon tuning through body bias clustering.
- Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye:
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.
- Xiaoji Ye, Peng Li, Frank Liu:
Practical variation-aware interconnect delay and slew analysis for statistical timing verification.
- Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao:
Analysis and modeling of CD variation for statistical static timing.
from dual to multi to many core - opportunities and challenges for supporting the new exponential
UML and SystemC for industrial ESL design - basic principles and applications
Efficient delay test generation
Power grid analysis and design
Optimization techniques for different target technologies
Placement and floorplanning
Digital and RF test and reliability
Statistical timing analysis
- Sari Onaissi, Farid N. Najm:
A linear-time approach for static timing analysis covering all process corners.
- Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula:
A framework for statistical timing analysis using non-linear delay and slew models.
- Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis.
- Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester:
A new statistical max operation for propagating skewness in statistical timing analysis.
Power and performance optimizations on system level design
Analog simulation and verification
Self adaptation and physical awareness in high-level synthesis
Advances in performance modeling for interconnect and memory
design and CAD challenges in 45nm CMOS and beyond - from front to back
Analog design automation techniques
Challenges on system level interconnection
- Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing application-specific networks on chips with floorplan information.
- Gunar Schirner, Rainer Dömer:
Fast and accurate transaction level models using result oriented modeling.
- Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling:
Optimal memoryless encoding for low power off-chip data buses.
timing, noise, and power
Timing and power analysis
- Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou:
A timing dependent power estimation framework considering coupling.
- Kenneth S. Stevens, Florentin Dartu:
Algorithms for MIS vector generation and pruning.
- Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng:
Timing model reduction for hierarchical timing analysis.
- Sean X. Shi, Peng Yu, David Z. Pan:
A unified non-rectangular device and circuit simulation model for timing and power.
Thermal and variability issues in architectures
automation in mixed-signal design - reality check and the nano challenge
Emerging topics in signal integrity and reliability
- Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
An analytical model for negative bias temperature instability.
- Hossein Asadi, Mehdi Baradaran Tahoori:
Soft error derating computation in sequential circuits.
- Rajeev R. Rao, David Blaauw, Dennis Sylvester:
Soft error reduction in combinational logic using gate resizing and flipflop selection.
- Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo:
Current path analysis for electrostatic discharge protection.
Fault-tolerant energy minimization techniques for real-time embedded systems
Emerging issues in contemporaneous system level design
Clock and buffer synthesis
Thermal analysis for the nano scale
Advances in embedded system design
Architectural design techniques for high performance and robustness
Manufacturability and power in layout
emerging nanoelectronics - prospects, state of the art and opportunities for CAD
Technology driven layout methodologies
Novel FPGA architectures, techniques and designs
- Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.
- Marvin Tom, David Leong, Guy G. Lemieux:
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.
- Xin Jia, Ranga Vemuri:
Studying a GALS FPGA architecture using a parameterized automatic design flow.
- David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky:
Conjoining soft-core FPGA processors.
Specification and architecture challenges in high-level synthesis
- Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
- Jason Cong, Yiping Fan, Wei Jiang:
Platform-based resource binding using a distributed register-file microarchitecture.
- Greg Stitt, Frank Vahid, Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C.
- Girish Venkataramani, Seth Copen Goldstein:
Leveraging protocol knowledge in slack matching.
Defect tolerance for nanoscale architectures
Dynamic power management
Advances in model checking
Novel interconnect methodologies
- Hao Yu, Joanna Ho, Lei He:
Simultaneous power and thermal integrity driven via stapling in 3D ICs.
- Alberto Fazzi, L. Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri:
Yield prediction for 3D capacitive interconnections.
- Renshen Wang, Rui Shi, Chung-Kuan Cheng:
Layer minimization of escape routing in area array packaging.
- Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson:
Network coding for routability improvement in VLSI.
integrating nanoelectronics, biotechnology and MEMS/NEMS
- Bernhard E. Boser:
From micro to nano: MEMS as an interface to the nano world.
- Ann Witvrouw:
CMOS-MEMS integration: why, how and what?
- Richard A. Kiehl:
Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures.
- Vladimir Bulovic, Kyungbum Kevin Ryu, Charles Sodini, Ioannis Kymissis, Annie Wang, Ivan Nausieda, Akintunde Ibitayo Akinwande:
Molecular organic electronic circuits.
- Conor F. Madigan, Vladimir Bulovic:
Organic electronic device modeling at the nanoscale.
variability and yield improvement:
rules, models, and characterization
Model order reduction and parametric analysis
Design and modeling of molecular-scale systems
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