ICCAD 2007: San Jose, California, USA

Advances in parasitic extraction and variability modeling

Networks-on-Chip and latency-insensitive systems

Power grid analysis

Synthesis and verification of quantum circuits

Connecting physical challenges and design approaches

Analytical techniques for physical optimization

Logic synthesis

Memory optimization and system-level timing

Resilient and regular circuits

3-D integration challenges

Applications of SAT and QBF

Physical synthesis comes of age

High quality test cases for verification

Advances in embedded systems

Can nano-photonic silicon circuits become an intra-chip interconnect technology?

Scaling formal verification

Advances in statistical timing analysis and optimization

Sequential synthesis and FPGA mapping

Advances in routing and clock design

Improving delay test generation and performance predictors

High level synthesis

Analog circuit optimization

Global routing

Test compression and test power

Gate level physical synthesis

Interconnect modeling and optimization

Formal verification at higher levels of abstraction

Floorplanning

System-level synthesis and interconnect design

Advances in model order reduction techniques for interconnect analysis

Mosfet modeling for 45nm & beyond

Voltage assignment in floorplanning

Variation tolerant circuits

Advanced models for static timing analysis

Variation aware timing verification

Reliability driven modeling and analysis for deep submicron technologies

Design automation and defect tolerance techniques for emerging technologies

Leakage power reduction

Power modeling and optimization

Improving planarity and patterning

Model order reduction for parameterized and non-linear systems