San Jose, California, USA 2009 International Conference on Computer-Aided Design (ICCAD'09), November 2-5, 2009, San Jose, CA, USA.
Advances in Routing
- Liang Li, Zaichen Qian, Evangeline F. Y. Young:
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree.
- Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Jung-Hung Weng:
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection.
- Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak:
How to consider shorts and guarantee yield rate improvement for redundant wire insertion.
- Tsun-Ming Tseng, Mango Chia-Tso Chao, Chien Pang Lu, Chen Hsing Lo:
Power-switch routing for coarse-grain MTCMOS technologies.
Scheduling Techniques for Low Power
Advances in Test Efficiency
- Mingjing Chen, Alex Orailoglu:
Scan power reduction in linear test data compression scheme.
- Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Compacting test vector sets via strategic use of implications.
- Jiniun Xionq, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah:
Pre-ATPG path selection for near optimal post-ATPG process space coverage.
- Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.
Advances in FPGA Synthesis and Trustable
- Zhe Feng, Yu Hu, Lei He, Rupak Majumdar:
IPR: In-Place Reconfiguration for FPGA fault tolerance.
- Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia:
A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
- Rajat Subhra Chakraborty, Swarup Bhunia:
Security against hardware Trojan through a novel application of design obfuscation.
- Lang Lin, Wayne Burleson, Christof Paar:
MOLES: Malicious off-chip leakage enabled by side-channels.
- Yousra Alkabani, Farinaz Koushanfar:
Consistency-based characterization for IC Trojan detection.
Design Automation for Biological Systems
- Noah Ollikainen, Ellen Sentovich, Carlos Coelho, Andreas Kuehlmann, Tanja Kortemme:
SAT-based protein design.
- Adam Shea, Marc D. Riedel, Brian Fett, Keshab K. Parhi:
Synthesizing sequential register-based computation with biochemistry.
- Ehsan Ullah, Kyongbum Lee, Soha Hassoun:
An algorithm for identifying dominant-edge metabolic pathways.
- Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho:
A contamination aware droplet routing algorithm for digital microfluidic biochips.
Analysis and Mitigation of Transient and Permanent Failures
Emerging Topics in Test and Reliability
- Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim:
Pre-bond testable low-power clock tree design for 3D stacked ICs.
- Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak:
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.
- Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores.
- Yanjing Li, Onur Mutlu, Subhasish Mitra:
Operating system scheduling for efficient online self-test in robust systems.
Timing Closure and Design Robustness
Routing in Alternative Technologies
- Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Exact route matching algorithms for analog and mixed signal integrated circuits.
- Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng:
An efficient pre-assignment routing algorithm for flip-chip designs.
- Tan Yan, Hui Kong, Martin D. F. Wong:
Optimal layer assignment for escape routing of buses.
- Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang:
Pad assignment for die-stacking System-in-Package design.
Emerging Design and Memory Technologies
Analytical Advances in Physical Synthesis
- Yujia Feng, Shiyan Hu:
The epsilon-approximation to discrete VT assignment for leakage power minimization.
- Tony F. Chan, Jason Cong, Eric Radke:
A rigorous framework for convergent net weighting schemes in timing-driven placement.
- Zuochang Ye, Zhiping Yu:
An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis.
Thermal-Aware Management Techniques for Multi-Core Architectures
Statistical Timing Analysis and Its Application
Congestion Driven Placement
New Applications in Logic Synthesis
Advanced Modeling and Simulation Methods
Characterization and Compensation of Variability
Policies and Methods for Low Power
Emerging Memory Technologies
- Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies.
- Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong:
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
- Yenpo Ho, Garng M. Huang, Peng Li:
Nonvolatile memristor memory: Device characteristics and design implications.
- Yong Zhang, Peng Li:
Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification.
Advanced Device Reliability and Modeling
- Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif:
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
- Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee:
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization.
- Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao:
Modeling of layout-dependent stress effect in CMOS design.
- Jiying Xue, Zuochang Ye, Yangdong Deng, Hongrui Wang, Liu Yang, Zhiping Yu:
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization.
Clock Optimization and Parallel Algorithm in EDA
Analysis and Optimization of Network-On-Chip and Multiprocessor SOC
- Yue Qian, Zhonghai Lu, Wenhua Dou:
From 2D to 3D NoCs: A case study on worst-case communication performance.
- Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and efficient performance analysis approach based on queuing model for network on chip.
- Nikita Nikitin, Jordi Cortadella:
A performance analytical model for Network-on-Chip with constant service time routers.
- Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad:
A method for calculating hard QoS guarantees for Networks-on-Chip.
- Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid:
Task management in MPSoCs: An ASIP approach.
Yield Estimation and Optimization for SRAMs
- Javid Jaffari, Mohab Anis:
Adaptive sampling for efficient failure probability analysis of SRAM cells.
- Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das:
Yield estimation of SRAM circuits using "Virtual SRAM Fab".
- Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky:
Mitigation of intra-array SRAM variability using adaptive voltage architecture.
Thermal Modeling and Analysis at Chip and Platform Levels
- Young-Joon Lee, Rohan Goel, Sung Kyu Lim:
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs.
- Donghwa Shin, Jihun Kim, Naehyuck Chang, Jinhang Choi, Sung Woo Chung, Eui-Young Chung:
Energy-optimal dynamic thermal management for green computing.
- Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard Smith, Kaustav Banerjee:
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies.
Performance and Power Issues in Embedded System-Level Design
- Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage.
- Jason Cong, Wei Jiang, Bin Liu, Yi Zou:
Automatic memory partitioning and scheduling for throughput and power optimization.
- Hengyu Long, Yongpan Liu, Yiqun Wang, Robert P. Dick, Huazhong Yang:
Battery allocation for wireless sensor network lifetime maximization under cost constraints.
Biological Circuits and Systems
Statistical Simulation and Optimization of Serial Link and Wordlength
Parasitic Extraction, Modeling, and Reduction Techniques
- Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia:
Decoupling capacitance efficient placement for reducing transient power supply noise.
- Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel:
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction.
- Ritochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala:
Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives.
- Zheng Zhang, Chi-Un Lei, Ngai Wong:
GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems.
- Zuochang Ye, Luis Miguel Silveira, Joel R. Phillips:
Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil.
Advanced Boolean Techniques in Logic Synthesis
Power 7 - Verification Challenges of a High-End 8-Core Microprocessor
Last update Thu May 23 16:59:14 2013
CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page