ICCAD 2011: San Jose, California, USA

• Georg Sigl:
  Keynote address: Design of secure systems - Where are the EDA tools? 1
  
• Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan:
  Layout decomposition for triple patterning lithography. 1-8
  
• Xiaoping Tang, Minsik Cho:
  Optimal layout decomposition for double patterning technology. 9-13
  
• Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
  A framework for double patterning-enabled design. 14-20
  
• Xuebei Yang, Kartik Mohanram:
  Unequal-error-protection codes in SRAMs for mobile multimedia applications. 21-27
  
• Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao:
  Detecting stability faults in sub-threshold SRAMs. 28-33
  
• Feng Yuan, Xiao Liu, Qiang Xu:
  Pseudo-functional testing for small delay defects considering power supply noise effects. 34-39
  
• Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel:
  A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding. 40-47
  
• Jishen Zhao, Cong Xu, Yuan Xie:
  Bandwidth-aware reconfigurable cache design with hybrid memory technologies. 48-55
  
• Hui Zhao, Akbar Sharifi, Shekhar Srikantaiah, Mahmut T. Kandemir:
  Feedback control based cache reliability enhancement for emerging multicores. 56-62
  
• Rasit Onur Topaloglu, Benedict R. Gaster:
  GPU programming for EDA with OpenCL. 63-66
  
• Myung-Chul Kim, Jin Hu, Dongjin Lee, Igor L. Markov:
  A SimPLR method for routability-driven placement. 67-73
  
• Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young:
  Ripple: An effective routability-driven placer by iterative cell movement. 74-79
  
• Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang:
  Routability-driven analytical placement for mixed-size circuit designs. 80-84
  
• Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu:
  PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. 85-90
  
• Dimitri de Jonghe, Georges G. E. Gielen:
  Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. 91-94
  
• Vladimir Zolotov, Jinjun Xiong:
  Optimal statistical chip disposition. 95-102
  
• Artem Rogachev, Lu Wan, Deming Chen:
  Temperature aware statistical static timing analysis. 103-110
  
• Bing Li, Ning Chen:
  Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. 111-117
  
• Mahmut T. Kandemir, Shekhar Srikantaiah, Seung Woo Son:
  Improving shared cache behavior of multithreaded object-oriented applications in multicores. 118-125
  
• Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran:
  CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. 126-133
  
• Praveen Yedlapalli, Emre Kultursay, Mahmut T. Kandemir:
  Cooperative parallelization. 134-141
  
• Wei Ding, Yuanrui Zhang, Jun Liu, Mahmut T. Kandemir:
  Optimizing data locality using array tiling. 142-149
  
• Jason Cong, Karthik Gururaj:
  Assuring application-level correctness against soft errors. 150-157
  
• Krishnendu Chakrabarty, Gary Dispoto, Rick Bellamy, Jun Zeng:
  The role of EDA in digital print automation and infrastructure optimization. 158-161
  
• Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar:
  Toward efficient spatial variation decomposition via sparse regression. 162-169
  
• Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal:
  REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. 170-177
  
• Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel:
  Accelerating aerial image simulation with GPU. 178-184
  
• Jason Cong, Peng Zhang, Yi Zou:
  Combined loop transformation and hierarchy allocation for data reuse optimization. 185-192
  
• Seokhyun Lee, Kiyoung Choi:
  High-level synthesis with distributed controller for fast timing closure. 193-199
  
• Elena Dubrova:
  Synthesis of parallel binary machines. 200-206
  
• Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan:
  Chemical-mechanical polishing aware application-specific 3D NoC design. 207-212
  
• Ali Shafiee, Mahdy Zolghadr, Mohammad Arjomand, Hamid Sarbazi-Azad:
  Application-aware deadlock-free oblivious routing based on extended turn-model. 213-218
  
• Avinash Karanth Kodi, Randy Morris, Dominic DiTomaso, Ashwini Sarathy, Ahmed Louri:
  Co-design of channel buffers and crossbar organizations in NoCs architectures. 219-226
  
• Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra:
  Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. 227-230
  
• Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici:
  Alternative design methodologies for the next generation logic switch. 231-234
  
• Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang:
  Progress and outlook for STT-MRAM. 235
  
• Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Helen Li:
  Universal statistical cure for predicting memory loss. 236-239
  
• Guillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki:
  Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. 240-245
  
• Gilberto Medeiros-Ribeiro, Janice H. Nickel, J. Joshua Yang:
  Progress in CMOS-memristor integration. 246-249
  
• Yue Xu, Chris Chu:
  MGR: Multi-level global router. 250-255
  
• Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth:
  Congestion analysis for global routing via integer programming. 256-262
  
• Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao:
  High-quality global routing for multiple dynamic supply voltage designs. 263-269
  
• Cliff C. N. Sze:
  The future of clock network synthesis. 270
  
• Joseph N. Kozhaya, Phillip Restle, Haifeng Qian:
  Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. 271-275
  
• Ali M. El-Husseini, Matthew Morrise:
  Clocking design automation in Intel's Core i7 and future designs. 276-278
  
• Igor L. Markov, Dongjin Lee:
  Algorithmic tuning of clock trees and derived non-tree structures. 279-282
  
• Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li:
  Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. 283-289
  
• Xin Gao, Luca Macchiarulo:
  A jumper insertion algorithm under antenna ratio and timing constraints. 290-297
  
• Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy:
  Exploring high throughput computing paradigm for global routing. 298-305
  
• Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang:
  Escape routing for staggered-pin-array PCBs. 306-309
  
• Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa:
  Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. 310-317
  
• Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan:
  The STeTSiMS STT-RAM simulation and modeling system. 318-325
  
• Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis:
  Massively parallel programming models used as hardware description languages: The OpenCL case. 326-333
  
• Jeffrey L. Krichmar, Nikil Dutt, Jayram Moorkanikara Nageswaran, Micah Richert:
  Neuromorphic modeling abstractions and simulation of large-scale cortical networks. 334-338
  
• Yu Wang, Mo Xu, Ling Ren, Xiaorui Zhang, Di Wu, Yong He, Ningyi Xu, Huazhong Yang:
  A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis. 339-344
  
• Miao Hu, Hai Li, Robinson E. Pino:
  Fast statistical model of TiO2 thin-film memristor and design implication. 345-352
  
• Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif:
  Accelerated statistical simulation via on-demand Hermite spline interpolations. 353-360
  
• Ting Mei, Heidi Thornquist, Eric R. Keiter, Scott A. Hutchinson:
  Structure preserving reduced-order modeling of linear periodic time-varying systems. 361-366
  
• David Amsallem, Jaijeet S. Roychowdhury:
  ModSpec: An open, flexible specification framework for multi-domain device modelling. 367-374
  
• Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets:
  Delay optimization using SOP balancing. 375-382
  
• Shao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang:
  Match and replace - A functional ECO engine for multi-error circuit rectification. 383-388
  
• Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang:
  Towards completely automatic decoder synthesis. 389-395
  
• Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang:
  On rewiring and simplification for canonicity in threshold logic circuits. 396-403
  
• ShengYu Shen, Ying Qin, Jianmin Zhang:
  Inferring assertion for complementary synthesis. 404-411
  
• Sangwoo Han, Joohee Choung, Byung-Su Kim, Bong Hyun Lee, Hungbok Choi, Juho Kim:
  Statistical aging analysis with process variation consideration. 412-419
  
• Changhao Yan, Sheng-Guo Wang, Xuan Zeng:
  A new method for multiparameter robust stability distribution analysis of linear analog circuits. 420-427
  
• Jyothi Bhaskarr Velamala, Venkatesa Ravi, Yu Cao:
  Failure diagnosis of asymmetric aging under NBTI. 428-433
  
• Zahra Lak, Nicola Nicolici:
  In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. 434-441
  
• Rong Ye, Feng Yuan, Qiang Xu:
  Online clock skew tuning for timing speculation. 442-447
  
• Tsung-Wei Huang, Tsung-Yi Ho, Krishnendu Chakrabarty:
  Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips. 448-455
  
• Yehua Su, Wenjing Rao:
  Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously. 456-462
  
• Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie:
  Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. 463-470
  
• Yaojun Zhang, Xiaobin Wang, Yiran Chen:
  STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. 471-477
  
• Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
  2011 TAU power grid simulation contest: Benchmark suite and results. 478-481
  
• Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
  PowerRush: A linear simulator for power grid. 482-487
  
• Zhiyu Zeng, Tong Xu, Zhuo Feng, Peng Li:
  Fast static analysis of power grids: Algorithms and implementations. 488-493
  
• Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang:
  On the preconditioner of conjugate gradient method - A power grid simulation perspective. 494-497
  
• Amith Singhee:
  PTrace: Derivative-free local tracing of bicriterial design tradeoffs. 498-502
  
• Walter James Condley, Xuchu Hu, Matthew R. Guthaus:
  A methodology for local resonant clock synthesis using LC-assisted local clock buffers. 503-506
  
• Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu:
  A corner stitching compliant B^∗-tree representation and its applications to analog placement. 507-511
  
• Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang:
  Heterogeneous B^∗-trees for analog placement with symmetry and regularity considerations. 512-516
  
• Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen:
  Fast analog layout prototyping for nanometer design migration. 517-522
  
• Zheng Zhang, Ibrahim M. Elfadel, Luca Daniel:
  Model order reduction of fully parameterized systems by recursive least square optimization. 523-530
  
• Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
  Fast poisson solver preconditioned method for robust power grid analysis. 531-536
  
• Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
  Modeling and estimation of power supply noise using linear programming. 537-542
  
• Xueqian Zhao, Jia Wang, Zhuo Feng, Shiyan Hu:
  Power grid analysis with hierarchical support graphs. 543-547
  
• Xuanxing Xiong, Jia Wang:
  Vectorless verification of RLC power grids with transient current constraints. 548-554
  
• Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim:
  Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. 555-562
  
• Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim:
  Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. 563-570
  
• Di-an Li, Malgorzata Marek-Sadowska:
  Variation-aware electromigration analysis of power/ground networks. 571-576
  
• Seokjoong Kim, Matthew R. Guthaus:
  Low-power multiple-bit upset tolerant memory optimization. 577-581
  
• Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He:
  Mitigating FPGA interconnect soft errors by in-place LUT inversion. 582-586
  
• Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour:
  Debugging with dominance: On-the-fly RTL debug solution implications. 587-594
  
• Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco:
  Simulation-based signal selection for state restoration in silicon debug. 595-601
  
• Bo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang (Ric) Huang:
  Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. 602-607
  
• Ryan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda:
  Identifying the optimal energy-efficient operating points of parallel workloads. 608-615
  
• Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
  System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. 616-623
  
• Younghyun Kim, Sangyoung Park, Yanzhi Wang, Qing Xie, Naehyuck Chang, Massimo Poncino, Massoud Pedram:
  Balanced reconfiguration of storage banks in a hybrid electrical energy storage system. 624-631
  
• Dongjin Lee, Igor L. Markov:
  Multilevel tree fusion for robust clock networks. 632-639
  
• Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin:
  Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. 640-646
  
• Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang:
  Useful-skew clock optimization for multi-power mode designs. 647-650
  
• Jason Cong, Yuhui Huang, Bo Yuan:
  ATree-based topology synthesis for on-chip network. 651-658
  
• Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi:
  Formal verification of phase-locked loops using reachability analysis and continuization. 659-666
  
• Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan:
  MACACO: Modeling and analysis of circuits for approximate computing. 667-673
  
• Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang:
  Property-specific sequential invariant extraction for SAT-based unbounded model checking. 674-678
  
• Miroslav N. Velev, Ping Gao:
  Automatic formal verification of multithreaded pipelined microprocessors. 679-686
  
• Hao Qian, Yangdong Deng:
  Accelerating RTL simulation with GPUs. 687-693
  
• Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
  CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. 694-701
  
• Andrey Ayupov, Steven M. Burns:
  A trace compression algorithm targeting power estimation of long benchmarks. 702-707
  
• Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
  A theoretical probabilistic simulation framework for dynamic power estimation. 708-715
  
• Hai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta:
  Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management. 716-723
  
• Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu:
  Gate sizing and device technology selection algorithms for high-performance industrial designs. 724-731
  
• Junjun Gu, Gang Qu, Lin Yuan, Cheng Zhuo:
  Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization. 732-735
  
• Jia Wang, Xiaodao Chen, Chen Liao, Shiyan Hu:
  The approximation scheme for peak power driven voltage partitioning. 736-741
  
• Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
  Timing ECO optimization via Bézier curve smoothing and fixability identification. 742-746
  
• Vasileios Tenentes, Xrysovalantis Kavousianos:
  Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. 747-754
  
• Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco:
  Post-silicon bug diagnosis with inconsistent executions. 755-761
  
• Nathan Kupp, Haralampos-G. D. Stratigopoulos, Petros Drineas, Yiorgos Makris:
  On proving the efficiency of alternative RF tests. 762-767
  
• Xiaochun Yu, R. D. (Shawn) Blanton:
  Statistical defect-detection analysis of test sets using readily-available tester data. 768-773
  
• Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang:
  A robust architecture for post-silicon skew tuning. 774-778
  
• Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Li-Shiuan Peh:
  A low-swing crossbar and link generator for low-power networks-on-chip. 779-786
  
• Hui Zhao, Mahmut T. Kandemir, Wei Ding, Mary Jane Irwin:
  Exploring heterogeneous NoC design space. 787-793
  
• Eliyah Kilada, Kenneth S. Stevens:
  Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging. 794-801
  
• Sheng Wei, Ani Nahapetian, Miodrag Potkonjak:
  Robust passive hardware metering. 802-809
  
• Michael DeBole, Ahmed Al-Maashri, Matthew Cotter, Chi-Li Yu, Chaitali Chakrabarti, Vijaykrishnan Narayanan:
  A framework for accelerating neuromorphic-vision algorithms on FPGAs. 810-813
  

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