ICCD 1995: Austin, Texas, USA

Architecture/Algorithms Plenary

• Benjamin W. Wah, Arthur Ieumwananonthachai, Shu Yao, Ting Yu:
  Statistical generalization: theory and applications. 4-
  

Signal propagation in high-speed MCM circuits

• C. Truzzi, Eric Beyne, E. Ringoot, J. Peeters:
  Signal propagation in high-speed MCM circuits. 12-17
  
• Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai:
  Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel. 18-24
  
• Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito:
  A CMOS gate array with dynamic-termination GTL I/O circuits. 25-
  

Asynchronous Systems

• William F. Richardson, Erik Brunvand:
  Precise exception handling for a self-timed processor. 32-37
  
• Mark R. Greenstreet:
  Implementing a STARI chip. 38-43
  
• Kenneth Y. Yun, David L. Dill:
  A high-performance asynchronous SCSI controller. 44-
  

Embedded System Analysis

• Jean Paul Calvez, Olivier Pasquier:
  Performance assessment of embedded Hw/Sw systems. 52-57
  
• Ti-Yen Yen, Wayne Wolf:
  Performance estimation for real-time distributed embedded systems. 64-71
  
• Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea:
  Verifying the performance of the PCI local bus using symbolic techniques. 72-78
  
• Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu:
  Extending VLSI design with higher-order logic. 85-
  

Issues in Superscalar Processors

• Steven Wallace, Nirav Dagli, Nader Bagherzadeh:
  Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. 96-101
  
• Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa:
  A superscalar RISC processor with pseudo vector processing feature. 102-109
  
• John-David Wellman, Edward S. Davidson:
  The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. 110-
  

SPARC Design Methodologies

• Alexander Dalal, Lavi Lev, Sundari Mitra:
  Design of an efficient power distribution network for the UltraSPARC-I microprocessor. 118-123
  
• H. Hao, K. Bhabuthmal:
  Clock controller design in SuperSPARC II microprocessor. 124-129
  
• Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor:
  Incas: a cycle accurate model of UltraSPARC. 130-137
  

Simulation

• Anirudh Devgan:
  Accurate device modeling techniques for efficient timing simulation of integrated circuits. 138-143
  
• Jay K. Adams, John Alan Miller, Donald E. Thomas:
  Execution-time profiling for multiple-process behavioral synthesis. 144-149
  
• Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller:
  Emulation verification of the Motorola 68060. 150-
  

Design for Testability

• Joan Carletta, Christos A. Papachristou:
  Testability analysis and insertion for RTL circuits based on pseudorandom BIST. 162-167
  
• Yu Fang, Alexander Albicki:
  Efficient testability enhancement for combinational circuit. 168-179
  
• Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
  Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. 173-179
  
• Franco Fummi, Donatella Sciuto, M. Serro:
  Synthesis for testability of large complexity controllers. 180-
  

PowerPC(tm)

• Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore:
  The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. 196-203
  
• Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington:
  A high performance bus and cache controller for PowerPC multiprocessing systems. 204-211
  
• Charles P. Roth, Frank E. Levine, Edward H. Welbon:
  Performance monitoring on the PowerPC 604 microprocessor. 212-
  

Floor Planning & Placement

• Kai-Yuan Chao, D. F. Wong:
  Thermal placement for high-performance multichip modules. 218-223
  
• Glenn Holt, Akhilesh Tyagi:
  EPNR: an energy-efficient automated layout synthesis package. 224-229
  
• Vinod Narayananan, David LaPotin, Rajesh K. Gupta, Gopalakrishnan Vijayan:
  PEPPER - a timing driven early floorplanner. 230-235
  
• Jin-Tai Yan:
  Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. 236-
  

Combinational and Sequential Logic Optimization

• Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul:
  An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. 244-249
  
• Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Implicit state minimization of non-deterministic FSMs. 250-257
  
• Chantal Ykman-Couvreur, Bill Lin:
  Efficient state assignment framework for asynchronous state graphs. 692-
  

Massively Parallel Processing Interconnects

• Peter A. Franaszek, Christos J. Georgiou, Chung-Sheng Li:
  Adaptive routing in Clos networks. 266-270
  
• Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward:
  Rational clocking [digital systems design]. 271-278
  
• T. Yokota, H. Matsuoka, K. Okamoto, H. Hirono, A. Hori, S. Sakai:
  A prototype router for the massively parallel computer RWC-1. 279-
  

Test Pattern Generation

• Stefan Radtke, Jens Bargfrede, Walter Anheier:
  Distributed automatic test pattern generation with a parallel FAN algorithm. 698-
  
• Abdel-Fattah Yousif, Jun Gu:
  Concurrent automatic test pattern generation algorithm for combinational circuits. 286-291
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Test generation for multiple state-table faults in finite-state machines. 292-
  

Caching Strategies

• Stephen J. Walsh, John A. Board:
  Pollution control caching. 300-
  
• Robert Yung, Neil C. Wilhelm:
  Caching processor general registers. 307-312
  
• Murali Kadiyala, Laxmi N. Bhuyan:
  A dynamic cache sub-block design to reduce false sharing. 313-
  

Embedded System Architecture & Case Studies

• Stuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin:
  A programmable routing controller for flexible communications in point-to-point networks. 320-331
  
• Jean-Paul Theis, Lothar Thiele:
  POM: a processor model for image processing. 326-331
  
• Andrew Wolfe:
  A case study in low-power system-level design. 332-
  

ATM and High-Speed Networking Alternatives

• Jin Li, Chuan-lin Wu:
  A novel architecture for an ATM switch. 340-345
  
• Steven E. Butner, David A. Skirmont:
  Architecture and design of a 40 gigabit per second ATM switch. 352-
  

Routing & Extraction

• Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs:
  Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. 360-365
  
• Jin-Tai Yan:
  An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. 366-371
  
• Yao-Wen Chang, D. F. Wong, C. K. Wong:
  FPGA global routing based on a new congestion metric. 372-
  

Asynchronous Datapaths

• Bret Stott, Dave Johnson, Venkatesh Akella:
  Asynchronous 2-D discrete cosine transform core processor. 380-385
  
• Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang:
  A self-timed redundant-binary number to binary number converter for digital arithmetic processors. 386-
  

FPGA - Synthesis

• Yao-Wen Chang, D. F. Wong, C. K. Wong:
  Design and analysis of FPGA/FPIC switch modules. 394-401
  
• Shashidhar Thakur, D. F. Wong:
  Simultaneous area and delay minimum K-LUT mapping for K-exact networks. 402-408
  
• Aiguo Lu, Erik L. Dagless, Jonathan M. Saul:
  DART: delay and routability driven technology mapping for LUT based FPGAs. 409-414
  
• Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose:
  Logic synthesis for a single large look-up table. 415-
  

Design & Test Plenary

• Sudhakar M. Reddy:
  Testing-what's missing? An incomplete list of challenges. 426-
  

Topics in High-Level Synthesis

• Ivan P. Radivojevic, Forrest Brewer:
  Analysis of conditional resource sharing using a guard-based control representation. 434-445
  
• Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao:
  Multi-dimensional interleaving for time-and-memory design optimization. 440-445
  
• Srinivas Katkoori, Nand Kumar, Ranga Vemuri:
  High level profiling based low power synthesis technique. 446-
  

Low Power and High-Performance Circuits

• Chuan-Yu Wang, Kaushik Roy:
  Control unit synthesis targeting low-power processors. 454-
  
• Kala Srivatsan, Chaitali Chakrabarti, Lori Lucke:
  Low power data format converter design using semi-static register allocation. 460-465
  
• H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto:
  A 13.3ns double-precision floating-point ALU and multiplier. 466-
  

Arithmetic Modules

• Hosahalli R. Srinivas, Keshab K. Parhi:
  A floating point radix 2 shared division/square root chip. 472-478
  
• Tzu-Hsi Pan, Hyon-Sok Kay, Youngsun Chun, Chin-Long Wey:
  High-radix SRT division with speculation of quotient digits . 479-
  
• Michael J. Schulte, Earl E. Swartzlander Jr.:
  A coprocessor for accurate and reliable numerical computations. 686-
  

Architectures for Signal Processors

• Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta:
  Special purpose FPGA for high-speed digital telecommunication systems. 486-491
  
• Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang:
  VLSI design of densely-connected array processors. 492-497
  
• Santanu Dutta, Wayne Wolf, Andrew Wolfe:
  VLSI issues in memory-system design for video signal processors. 498-
  

Memory System Performance

• Farnaz Mounes-Toussi, David J. Lilja:
  Write buffer design for cache-coherent shared-memory multiprocessors. 506-511
  
• Chi-Hung Chi, Siu-Chung Lau:
  Reducing data access penalty using intelligent opcode-driven cache prefetching. 512-517
  
• Aaron Goldberg, John A. Trotter:
  Interrupt-based hardware support for profiling memory system performance. 518-
  

Emerging Technologies for Processor Verification

• Miriam Leeser, John W. O'Leary:
  Verification of a subtractive radix-2 square root algorithm and implementation. 526-531
  
• Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham:
  Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. 532-537
  
• David Cyrluk, Mandayam K. Srivas:
  Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification. 538-
  

Memory Architectures for Signal Processing

• Martin C. Herbordt, Charles C. Weems:
  An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. 546-551
  
• Eddy de Greef, Francky Catthoor, Hugo De Man:
  Memory organization for video algorithms on programmable signal processors. 552-557
  
• Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito:
  SSM-MP: more scalability in shared-memory multi-processor. 558-
  

Novel Design Concepts

• Menghui Zheng, Alexander Albicki:
  Low power and high speed multiplication design through mixed number representations. 566-576
  
• Tan-Li Chou, Kaushik Roy:
  Estimation of sequential circuit activity considering spatial and temporal correlations. 577-
  

FSM Verification

• Ajay J. Daga, William P. Birmingham:
  A symbolic-simulation approach to the timing verification of interacting FSMs. 584-589
  
• Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal:
  Incremental methods for FSM traversal. 590-
  
• Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain:
  Extraction of finite state machines from transistor netlists by symbolic simulation. 596-601
  
• Rolf Drechsler, Bernd Becker:
  Dynamic minimization of OKFDDs. 602-
  

Fault Simulation

• Minesh B. Amin, Bapiraju Vinnakota:
  Data parallel fault simulation. 610-615
  
• Steven Parkes, Prithviraj Banerjee, Janak H. Patel:
  A parallel algorithm for fault simulation based on PROOFS . 616-
  
• Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda:
  Statistics on concurrent fault and design error simulation. 622-627
  
• Michael S. Hsiao, Janak H. Patel:
  A new architectural-level fault simulation using propagation prediction of grouped fault-effects. 628-
  

Application-Specific Processors

• Ram K. Krishnamurthy, Ramalingam Sridhar:
  A CMOS wave-pipelined image processor for real-time morphology . 638-
  
• Hyesook Lim, Earl E. Swartzlander Jr.:
  An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . 644-649
  
• Abdel Ejnioui, N. Ranganathan:
  Systolic algorithms for tree pattern matching. 650-702
  
• Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau:
  Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. 703-
  

Performance Driven Synthesis

• Hirendu Vaishnav, Massoud Pedram:
  Logic extraction based on normalized netlengths. 658-663
  
• Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai:
  Transformation of min-max optimization to least-square estimation and application to interconnect design optimization. 664-670
  
• Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng:
  Simple tree-construction heuristics for the fanout problem . 671-679
  
• Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray:
  Concurrent timing optimization of latch-based digital systems. 680-
  

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