ICCD 2001:
Austin, Texas, USA
19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings.
IEEE Computer Society 2001, ISBN 0-7695-1200-3 
Keynote Addresses
- Karl-Thomas Neumann:
The In-Car Computing Network: An Embedded Systems Challenge.
3-3
- John Paul Shen:
Clear and Present Tensions in Microprocessor Design.
4-4
- Lee M. Harrison:
Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry.
5-8
Asynchronous Techniques
Architectural Modeling:
Performance and Power Analysis
Caching
Simulation Based Verification
Modeling of Capacitance and Crosstalk Noise
Improving the Performance of Caching Structures
Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
- Irith Pomeranz, Sudhakar M. Reddy:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
142-147
- Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
148-153
- Dong Xiang, Yi Xu:
Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement.
154-160
Computer Arithmetic
Circuit Sizing and Optimization
Clocking and Time-Domain Measurements
Processor Microarchitecture
Invited Session:
Taming Tons of Gigabytes:
Innovations in Disk Drive Electronics
Energy Efficiency Caches and Multiport Cache Structures
Control by Simulation and On-line Checking
CAD Algorithms for Physical Design
Formal Methods for Property Verification and Equivalence Verification
Hardware Representation
Circuit Techniques
- Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Realization of Multiple-Output Functions by Reconfigurable Cascades.
388-393
- Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong:
A Low-Power Cache Design for CalmRISCTM-Based Systems.
394-399
- Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time.
400-405
- Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
406-414
DSP/Multimedia
- Deependra Talla, Lizy Kurian John:
Cost-effective Hardware Acceleration of Multimedia Applications.
415-424
- Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.
425-430
- Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis:
Low-Energy DSP Code Generation Using a Genetic Algorithm.
431-437
- Ali Manzak, Chaitali Chakrabarti:
Voltage Scaling for Energy Minimization with QoS Constraints.
438-446
Novel Architectures and ISA Extensions
- Ying Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan:
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.
447-452
- John Patrick McGregor, Ruby B. Lee:
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications.
453-461
- Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura:
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis.
462-467
- Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Use of Local Memory for Efficient Java Execution.
468-476
Poster Papers
- Afzal Hossain, Daniel J. Pease:
An Analytical Model for Trace Cache Instruction Fetch Performance.
477-480
- Jiang Hu, Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement.
481-483
- Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh:
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement.
484-487
- Felix Sheng-Ho Chang, Alan J. Hu:
Fast Specification of Cycle-accurate Processor Models.
488-492
- Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang:
A Performance Analysis of the Active Memory System.
493-496
- Kent E. Wires, Michael J. Schulte, James E. Stine:
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation.
497-500
- Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
An Algorithm for Dynamically Reconfigurable FPGA Placement.
501-504
- Pradeepsunder Ganesh, Charlie Chung-Ping Chen:
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments.
505-506
- James W. Hauser, Carla Neaderhouser Purdy:
Efficient Function Approximation for Embedded and ASIC Applications.
507-510
- Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park:
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking.
511-512
- Hong-Sik Kim, Jin-kyue Lee, Sungho Kang:
A Heuristic for Multiple Weight Set Generation.
513-514
- Prosenjit Chatterjee, Ganesh Gopalakrishnan:
towards A formal Model of Shared Memory Consistency for Intel ItaniumTM.
515-518
- Jennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom:
Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem.
519-522
- Halima El Naga, Jean-Luc Gaudiot:
MCOMA: A Multithreaded COMA Architecture.
523-525
- Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar:
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.
526-529
- Pipat Reungsang, Sun Kyu Park, Seh-Woong Jeong, Hyung-Lae Roh, Gyungho Lee:
Reducing Cache Pollution of Prefetching in a Small Data Cache.
530-533
- Rajesh Ramanujam, Murali Ravirala, Gyungho Lee:
Alloyed Path-pattern Scheme for Branch Prediction.
534-537
- Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Timing Characterization of Dual-edge Triggered Flip-flops.
538-541
- A. Murat Fiskiran, Ruby B. Lee:
Performance Impact of Addressing Modes on Encryption Algorithms.
542-545
- Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.
546-552
- James D. Z. Ma, Arvind Parihar, Lei He:
Pre-routing Estimation of Shielding for RLC Signal Integrity.
553-556
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