ICCD 2002: Freiburg, Germany

Keynote Addresses

• Justin R. Rattner:
  Supercomputing on a Chip: Evolution and Challenges.
  
• Raul Camposano:
  From IP to Platforms.
  
• Ulrich Ramacher:
  Application Specific Embedded Processors for Next Generation Communication Systems.
  

Computers in Media, Mobile and Servers

• Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui:
  Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. 2-7
  
• Ralf Kakerow:
  Low Power Design Methodologies for Mobile Communication. 8-13
  
• H. Peter Hofstee:
  Power-Constrained Microprocessor Design. 14-16
  
• Joerg Walter:
  Functional Verification of the IBM zSeries eServer z900 System. 17-
  

Physical Design

• Chung-Seok (Andy) Seo, Abhijit Chatterjee:
  A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect. 24-29
  
• Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
  Physical Planning Of On-Chip Interconnect Architectures. 30-35
  
• Stan Y. Liao, Narendra V. Shenoy, William Nicholls:
  An Efficient External-Memory Implementation of Region Query with Application to Area Routing. 36-41
  
• Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang:
  GPE: A New Representation for VLSI Floorplan Problem. 42-44
  
• Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
  A Standard-Cell Placement Tool for Designs with High Row Utilization. 45-
  

Verification

• Partha S. Roop, Arcot Sowmya, S. Ramesh:
  k-time Forced Simulation: A Formal Verification Technique for IP Reuse. 50-55
  
• Christoph Scholl, Bernd Becker:
  Checking Equivalence for Circuits Containing Incompletely Specified Boxes. 56-63
  
• Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
  Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. 64-69
  
• Hong Peng, Yassine Mokhtari, Sofiène Tahar:
  Environment Synthesis for Compositional Model Checking. 70-
  

Design ITRS 2001 - Issues and Solutions

• Patrick Groeneveld:
  Physical Design Challenges for Billion Transistor Chips. 78-83
  
• Kurt Keutzer, Sharad Malik, A. Richard Newton:
  From ASIC to ASIP: The Next Design Discontinuity. 84-90
  
• Surrendra Dudani, Jayant Nagda:
  High Level Functional Verification Closure. 91-
  

Data Path Elements for Multi-GHz Design

• Sumio Morioka, Akashi Satoh:
  A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. 98-103
  
• Alexander Taubin, Karl Fant, John McCardle:
  Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing. 104-111
  
• Eduardo A. C. da Costa, Sergio Bampi, José Monteiro:
  A New Architecture for Signed Radix-2m Pure Array Multipliers. 112-117
  
• Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev:
  A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. 118-121
  
• Tyler Thorp, Dean Liu:
  Analysis of Blocking Dynamic Circuits. 122-
  

Multimedia and and Arithmetic

• Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, Petri Liuha:
  Parallel Multiple-Symbol Variable-Length Decoding. 126-131
  
• José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
  Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. 132-137
  
• Huesung Kim, Arun K. Somani, Akhilesh Tyagi:
  Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs). 138-144
  
• Tomás Lang, Javier D. Bruguera:
  Floating-Point Fused Multiply-Add with Reduced Latency. 145-
  

Methodology Issues for High Performance Designs

• Louis Scheffer:
  Methodologies and Tools for Pipelined On-Chip Interconnect. 152-157
  
• Rita Yu Chen, Paul Yip, Georgios Konstadinidis, Andrew Demas, Fabian Klass, Rob Mains, Margaret Schmitt, Dina Bistry:
  Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design. 158-163
  
• B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain:
  A System-Level Solution to Domino Synthesis with 2 GHz Application. 164-
  

Low-Power Microarchitecture

• Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Kevin B. Theobald:
  Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. 174-179
  
• Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
  Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. 180-186
  
• Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami:
  A Low Energy Set-Associative I-Cache with Extended BTB. 187-
  

Design for Testability

• Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy:
  Don't-Care Identification on Specific Bits of Test Patterns. 194-199
  
• Michiko Inoue, Chikateru Jinno, Hideo Fujiwara:
  An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. 200-205
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. 206-209
  
• Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus:
  A Test Processor Concept for Systems-on-a-Chip. 210-
  

Sensor Networks: New Architecture and Synthesis Challenges

• Lewis Girod, Vladimir Bychkovskiy, Jeremy Elson, Deborah Estrin:
  Locating Tiny Sensors in Time and Space: A Case Study. 214-219
  
• Andreas Savvides, Mani B. Srivastava:
  A Distributed Computation Platform for Wireless Embedded Sensing. 220-225
  
• Jessica Feng, Farinaz Koushanfar, Miodrag Potkonjak:
  System-Architectures for Sensor Networks Issues, Alternatives, and Directions. 226-
  

Computer Systems Design and Applications I

• Zhijie Shi, Ruby B. Lee:
  Subword Sorting with Versatile Permutation Instructions. 234-241
  
• Murali Annavaram, Trung A. Diep, John Paul Shen:
  Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. 242-248
  
• Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang:
  Performance Enhancements to the Active Memory System. 249-
  

Analog Test and Dependability

• Sule Ozev, Alex Orailoglu:
  Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. 258-264
  
• I-De Huang, Sandeep K. Gupta, Melvin A. Breuer:
  Accurate and Efficient Static Timing Analysis with Crosstalk. 265-272
  
• Jacob Savir, Zhen Guo:
  On the Detectability of Parametric Faults in Analog Circuits. 273-276
  
• Andreas Steininger, Johann Vilanek:
  Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. 277-
  

The Imagine Processor

• Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany:
  The Imagine Stream Processor. 282-288
  
• Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles:
  VLSI Design and Verification of the Imagine Processor. 289-294
  
• John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally:
  Media Processing Applications on the Imagine Stream Processor. 295-302
  
• Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally:
  A Stream Processor Development Platform. 303-
  

Low Power Circuit Techniques

• Tadahiro Kuroda:
  Low-Power, High-Speed CMOS VLSI Design. 310-315
  
• Stephanie Augsburger, Borivoje Nikolic:
  Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction. 316-321
  
• Geun Rae Cho, Tom Chen:
  On The Impact of Technology Scaling On Mixed PTL/Static Circuits. 322-326
  
• Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai:
  Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. 327-
  

Cache Memories

• Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
  Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. 334-339
  
• Jinwoo Kim, Krishna V. Palem, Weng-Fai Wong:
  A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors. 340-347
  
• Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen:
  Trace Cache Performance Parameters. 348-355
  
• Terry Lyon, Eric Delano, Cameron McNairy, Dean Mulla:
  Data Cache Design Considerations for the Itanium^® 2 Processor. 356-
  

Processors in Automotive Systems

• Joachim Schlosser:
  Requirements for Automotive System Engineering Tools. 364-369
  
• Paolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
  Automotive Virtual Integration Platforms: Why's, What's, and How's. 370-378
  
• Paolo Giusto, Jean-Yves Brunel, Alberto Ferrari, Eliane Fourgeau, Luciano Lavagno, Barry O'Rourke, Alberto L. Sangiovanni-Vincentelli, Emanuele Guasto:
  Models of IP's for Automotive Virtual Integration Platforms. 379-
  

Power Management and High Level Synthesis

• David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland:
  Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. 382-387
  
• Sanjukta Bhanja, N. Ranganathan:
  Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. 388-390
  
• Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha:
  Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. 391-394
  
• Seda Ogrenci Memik, Farzan Fallah:
  Accelerated SAT-based Scheduling of Control/Data Flow Graphs. 395-
  

Speculative and Packet Oriented Architectures

• Carlos Molina, Antonio González, Jordi Tubella:
  Trace-Level Speculative Multithreaded Architecture. 402-407
  
• Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan:
  Speculative Trace Scheduling in VLIW Processors. 408-413
  
• Tomas Henriksson, Ulf Nordqvist, Dake Liu:
  Embedded Protocol Processor for Fast and Efficient Packet Reception. 414-
  

Interconnect Modeling and Analysis

• Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu:
  Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. 422-427
  
• Guoan Zhong, Cheng-Kok Koh:
  Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. 428-433
  
• Haitian Hu, Sachin S. Sapatnekar:
  Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. 434-
  

Issues in Processor Architecture

• Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi:
  Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. 442-445
  
• Ann Gordon-Ross, Frank Vahid:
  Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. 446-449
  
• Manfred Ley, Herbert Grünbacher:
  TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol. 450-453
  
• Aristides Efthymiou, Jim D. Garside:
  Adaptive Pipeline Depth Control for Processor Power-Management. 454-457
  
• Amirali Baniasadi, Andreas Moshovos:
  Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. 458-461
  
• Joshua J. Yi, David J. Lilja:
  Improving Processor Performance by Simplifying and Bypassing Trivial Computations. 462-
  

Low Power Test, Diagnosis

• Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
  A Low Power Pseudo-Random BIST Technique. 468-473
  
• Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
  Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. 474-479
  
• Baris Arslan, Alex Orailoglu:
  Fault Dictionary Size Reduction through Test Response Superposition. 480-
  

System Design Issues

• Ivan Blunno, Luciano Lavagno:
  Designing an Asynchronous Microcontroller Using Pipefitter. 488-493
  
• Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino:
  Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. 494-499
  
• Stefan Ihmor, Markus Visarius, Wolfram Hardt:
  A Design Methodology for Application-Specific Real-Time Interfaces. 500-
  

Computer Systems Design and Applications II

• Stevan A. Vlaovic, Edward S. Davidson:
  TAXI: Trace Analysis for X86 Interpretation. 508-514
  
• Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
  Embedded Operating System Energy Analysis and Macro-Modeling. 515-520
  
• Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau:
  SIMD Extension to VLIW Multicluster Processors for Embedded Applications. 523-526
  
• Panit Watcharawitch, Simon W. Moore:
  JMA: The Java-Multithreading Architecture for Embedded Processors. 527-
  

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