ICCD 2006: San Jose, CA, USA

• Welcome Message.
  
• Organizing Committee.
  
• Program Committee.
  
• Additional Reviewers.
  

Keynote Presentation

• William J. Dally:
  Computer Architecture in the Many-Core Era.
  

Microarchitecture Optimization

• Fei Gao, Suleyman Sair:
  Long-term Performance Bottleneck Analysis and Prediction.
  
• Weifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway:
  Speculative Code Value Specialization Using the Trace Cache Fill Unit.
  
• Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
  Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.
  
• Shuo Wang, Lei Wang:
  Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing.
  
• Chuanjun Zhang:
  A Low Power Highly Associative Cache for Embedded Systems.
  

1.2 Timing Analysis

• Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri:
  On the Improvement of Statistical Static Timing Analysis.
  
• Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
  FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
  
• Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier:
  Reduction of Crosstalk Pessimism using Tendency Graph Approach.
  
• Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan:
  Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.
  

1.3 Advanced Circuits and Interconnections

• Simon Hollis, Simon W. Moore:
  RasP: An Area-efficient, On-chip Network.
  
• Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
  Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
  
• Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri:
  CMOS Comparators for High-Speed and Low-Power Applications.
  
• Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara:
  Reconfigurable CAM Architecture for Network Search Engines.
  
• Karl Mohr, Lawrence Clark:
  Delay and Area Efficient First-level Cache Soft Error Detection and Correction.
  

2.1 Special Session on Nanotechnology - I

• Krishnendu Chakrabarty:
  Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD.
  

3.1 Technology-Aware Design

• Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum:
  Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.
  
• Subramanian Ramaswamy, Sudhakar Yalamanchili:
  Customizable Fault Tolerant Caches for Embedded Processors.
  
• Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang:
  Reduce Register Files Leakage Through Discharging Cells.
  
• Yi Ma, Huiyang Zhou:
  Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution.
  

3.2 Multiprocessors and Systems-on-Chip

• Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar:
  Dynamic Co-Processor Architecture for Software Acceleration on CSoCs.
  
• Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh:
  Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
  
• Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad:
  A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
  
• Sean Leventhal, Manoj Franklin:
  Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors.
  

3.3 Robust and Low-Power Design Styles

• Kimiyoshi Usami, Naoaki Ohkubo:
  A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.
  
• Kim Yaw Tong, Lawrence T. Pileggi:
  Synthesis of Regular Logic Bricks for Robust IC Design.
  
• Sanjay Pant, David Blaauw:
  An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.
  
• Zhiyi Yu, Bevan M. Baas:
  Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
  

Banquet - Keynote Speaker

• Fabio Angelillis:
  Scaling Manufacturability Software to Thousands of Processors.
  

Special Session on Interconnect

• Enno Wein:
  Scale in Chip Interconnect requires Network Technology .
  
• Uri Cummings:
  Interconnect Considerations For High Performance Network on Chip Designs.
  
• Drew Wingard:
  Addressing Multicore Communication Challenges Using NoC Technology.
  

5.1 Hardware and Software Scheduling Techniques

• Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, Guido Araujo:
  Clustering-Based Microcode Compression.
  
• Kuo-Su Hsiao, Chung-Ho Chen:
  Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling.
  
• Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería:
  An Enhancement for a Scheduling Logic Pipelined over two Cycles .
  

5.2 Nanoscale Modeling + Synthesis

• Saraju P. Mohanty, Elias Kougianos:
  Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates.
  
• Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
  Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
  
• Rasit Onur Topaloglu, Andrew B. Kahng:
  Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.
  

5.3 Power Issues in Test

• Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
  Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
  
• Ho Fai Ko, Nicola Nicolici:
  RTL Scan Design for Skewed-Load At-speed Test under Power Constraints.
  
• Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker:
  Power Droop Testing.
  
• Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
  Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
  

Special Session on Hardware Equivalence

• Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen:
  Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .
  
• Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili:
  Seqver : A Sequential Equivalence Verifier for Hardware Designs .
  
• Alan Hu:
  High-Level vs. RTL Combinational Equivalence: An Introduction.
  

7.1 Functional Verification - Advances and Applications

• Kameshwar Chandrasekar, Michael S. Hsiao:
  Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique.
  
• Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten:
  Requirements and Concepts for Transaction Level Assertions.
  
• Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
  Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.
  
• Charles H.-P. Wen, Onur Guzey, Li-C. Wang:
  Simulation-based functional test justification using a decision-digram-based Boolean data miner.
  

7.2 Application Specific Processing Elements

• Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner:
  FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.
  
• Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
  FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
  
• Tinoosh Mohsenin, Bevan M. Baas:
  Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
  
• Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi:
  An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
  

7.3 Physical Design

• Hailin Jiang, Malgorzata Marek-Sadowska:
  Power/ground supply network optimization for power-gating.
  
• Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
  A Pattern Generation Technique for Maximizing Power Supply Currents.
  
• Avijit Dutta, David Z. Pan:
  Partial Functional Manipulation Based Wirelength Minimization.
  
• Sungjae Kim, Eugene Shragowitz:
  Iterative-Constructive Standard Cell Placer for High Speed and Low Power.
  

8.1 Design Techniques and Methods

• Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
  Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths .
  
• Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi:
  Assertion-Based Microarchitecture Design for Improved Reliability.
  
• Xinmiao Zhang:
  High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding.
  

8.2 System On Chip Design

• Banit Agrawal, Timothy Sherwood:
  Guiding Architectural SRAM Models.
  
• Jinwen Xi, Peixin Zhong:
  A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models.
  
• Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
  Reliability Support for On-Chip Memories Using Networks-on-Chip.
  
• Shaobo Liu, Qinru Qiu, Qing Wu:
  Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems.
  

8.3 Power-Efficient Systems

• Chuanjun Zhang:
  A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems.
  
• Xiaofang Wang, Sotirios G. Ziavras:
  System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors.
  
• Frederick A. Ware, Craig Hampel:
  Improving Power and Data Efficiency with Threaded Memory Modules.
  

9.1 Improving test quality

• Chia Yee Ooi, Hideo Fujiwara:
  A New Class of Sequential Circuits with Acyclic Test Generation Complexity.
  
• Erkan Acar, Sule Ozev:
  Efficient Testing of RF MIMO Transceivers Used in WLAN Applications.
  
• Shideh Shahidi, Sandeep Gupta:
  A theory of Error-Rate Testing.
  
• Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun:
  Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.
  

9.2 Architectural Synthesis

• Hwisung Jung, Massoud Pedram:
  Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach.
  
• Fu-Chiung Cheng, Hung-Chi Wu:
  Design and Implementation of Software Objects in Hardware.
  
• Sourav Roy, Rajat Bhatia, Ashish Mathur:
  An accurate Energy estimation framework for VLIW Processor Cores.
  

10.1 Design Practice

• Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler:
  Design and Implementation of the TRIPS Primary Memory System.
  
• Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
  Implementation and Evaluation of On-Chip Network Architectures.
  
• Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang:
  Microarchitecture and Performance Analysis of Godson-2 SMT Processor.
  
• Satish Narayanasamy, Bruce Carneal, Brad Calder:
  Patching Processor Design Errors.
  

10.2 Architectural Support for Error Protection

• Nathan Sadler, Daniel Sorin:
  Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache.
  
• Yixin Shi, Sean Dempsey, Gyungho Lee:
  Architectural Support for Run-Time Validation of Control Flow Transfer.
  
• Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi:
  Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection.
  

11.1 Special Session on Nanotechnology - II

• R. Iris Bahar:
  Trends and Future Directions in Nano Structure Based Computing and Fabrication.
  

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