ICCD 2008: Lake Tahoe, CA, USA

Fault and error tolerance

• Thomas Panhofer, Werner Friesenbichler, Martin Delvai:
  Fault tolerant Four-State Logic by using Self-Healing Cells. 1-6
  
• Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram:
  Probabilistic error propagation in logic circuits using the Boolean difference calculus. 7-13
  
• Rajesh Garg, Sunil P. Khatri:
  A novel, highly SEU tolerant digital circuit design approach. 14-20
  

Tree Construction

• Iris Hui-Ru Jiang, Ming-Hua Wu:
  Power-state-aware buffered tree construction. 21-26
  
• Christian Fobel, Gary Gréwal:
  A parallel Steiner tree heuristic for macro cell routing. 27-33
  
• Iris Hui-Ru Jiang, Yen-Ting Yu:
  Configurable rectilinear Steiner tree construction for SoC and nano technologies. 34-39
  

Formal Verification

• Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes:
  Improving SAT-based Combinational Equivalence Checking through circuit preprocessing. 40-45
  
• Xueqi Cheng, Michael S. Hsiao:
  Ant Colony Optimization directed program abstraction for software bounded model checking. 46-51
  
• Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer:
  Propositional approximations for bounded model checking of partial circuit designs. 52-59
  

Application-Specific Processing Elements

• Jeff Pool, Anselmo Lastra, Montek Singh:
  Energy-precision tradeoffs in mobile Graphics Processing Units. 60-67
  
• Pankaj Bhagawat, Rajballav Dash, Gwan Choi:
  Dynamically reconfigurable soft output MIMO detector. 68-73
  
• Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado:
  Applying speculation techniques to implement functional units. 74-80
  
• Atif Hashmi, Mikko H. Lipasti:
  Accelerating search and recognition with a TCAM functional unit. 81-86
  
• Brian J. Hickmann, Michael J. Schulte, Mark A. Erle:
  Improved combined binary/decimal fixed-point multipliers. 87-94
  
• José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno:
  Architecture implementation of an improved decimal CORDIC method. 95-100
  

Clock Distribution

• Aida Todri, Malgorzata Marek-Sadowska:
  A study of reliability issues in clock distribution networks. 101-106
  
• Chunchen Liu, Junjie Su, Yiyu Shi:
  Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations. 107-113
  
• Vinayak Honkote, Baris Taskin:
  Custom rotary clock router. 114-119
  
• Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
  Safe clocking register assignment in datapath synthesis. 120-127
  
• Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
  Gate planning during placement for gated clock network. 128-133
  

Network-on-Chips

• Rohit Sunkam Ramanujam, Bill Lin:
  Near-optimal oblivious routing on three-dimensional mesh networks. 134-141
  
• Shan Yan, Bill Lin:
  Design of application-specific 3D Networks-on-Chip architectures. 142-149
  
• Ahmad Khonsari, Mohammad R. Aghajani, Arash Tavakkol, Mohammad Sadegh Talebi:
  Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic. 150-155
  
• Karthik Sabhanatarajan, Ann Gordon-Ross:
  A resource efficient content inspection system for next generation Smart NICs. 156-163
  
• Chen-Ling Chou, Radu Marculescu:
  Contention-aware application mapping for Network-on-Chip communication architectures. 164-169
  

Circuit design

• Kaijian Shi:
  Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities. 170-175
  
• Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham:
  Adaptive SRAM memory for low power and high yield. 176-181
  
• Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng:
  On-chip high performance signaling using passive compensation. 182-187
  
• Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann:
  A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. 188-193
  
• Hamed Abrishami, Safar Hatami, Massoud Pedram:
  Characterization and design of sequential circuit elements to combat soft error. 194-199
  
• Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie:
  Comparative analysis of NBTI effects on low power and high performance flip-flops. 200-205
  

SoC, Memory and Analog Testing

• Jason D. Lee, Rabi N. Mahapatra:
  In-field NoC-based SoC testing with distributed test vector storage. 206-211
  
• Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie:
  Test-access mechanism optimization for core-based three-dimensional SOCs. 212-218
  
• Jae Chul Cha, Sandeep K. Gupta:
  Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. 219-226
  
• Ender Yilmaz, Sule Ozev:
  Dynamic test scheduling for analog circuits for improved test quality. 227-233
  
• Mingjing Chen, Alex Orailoglu:
  Test cost minimization through adaptive test development. 234-239
  

Application-Specific Systems

• Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang:
  Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA. 240-247
  
• Zhibin Xiao, Bevan M. Baas:
  A high-performance parallel CAVLC encoder on a fine-grained many-core system. 248-254
  
• Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois:
  Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. 255-259
  
• Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao:
  Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. 260-265
  
• Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David:
  Application Specific Instruction set processor specialized for block motion estimation. 266-271
  
• Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo:
  Prototyping a hybrid main memory using a virtual machine monitor. 272-279
  

Best Paper Session

• Eren Kursun, Chen-Yong Cher:
  Variation-aware thermal characterization and management of multi-core architectures. 280-285
  
• Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai:
  Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective. 286-293
  
• David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
  Analysis and minimization of practical energy in 45nm subthreshold logic circuits. 294-300
  
• Kai-Chiang Wu, Diana Marculescu:
  Power-aware soft error hardening via selective voltage scaling. 301-306
  
• Ilya Wagner, Valeria Bertacco:
  Reversi: Post-silicon validation system for modern microprocessors. 307-314
  

VLSI signal processing

• Jeong-Ho Han, In-Cheol Park:
  Digital filter synthesis considering multiple adder graphs for a coefficient. 315-320
  
• Adnan Suleiman, Hani Saleh, Adel Hussein, David Akopian:
  A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications. 321-327
  
• Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga:
  Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264. 328-333
  
• Ali Namazi, Syed Askari, Mehrdad Nourani:
  Highly reliable A/D converter using analog voting. 334-339
  

Simulation and Reliability

• J. P. Grossman, John K. Salmon, Richard C. Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw:
  Hierarchical simulation-based verification of Anton, a special-purpose parallel machine. 340-347
  
• Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
  Post-silicon verification for cache coherence. 348-355
  
• Christian Hochberger, Alexander Weiss:
  Acquiring an exhaustive, continuous and real-time trace from SoCs. 356-362
  
• Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin:
  CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. 363-370
  

Multi-Threaded and Multi-Core Architectures

• Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer:
  Exploiting spare resources of in-order SMT processors executing hard real-time threads. 371-376
  
• Carsten Gremzow:
  Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design. 377-383
  
• Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song:
  A simple latency tolerant processor. 384-389
  
• Marius Grannæs, Magnus Jahre, Lasse Natvig:
  Low-cost open-page prefetch scheduling in chip multiprocessors. 390-396
  
• Arun A. Nair, Lizy K. John:
  Simulation points for SPEC CPU 2006. 397-403
  

VLSI Arithmetic

• Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
  Synthesis of parallel prefix adders considering switching activities. 404-409
  
• Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev:
  Conversion driven design of binary to mixed radix circuits. 410-415
  
• Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh:
  Systematic design of high-radix Montgomery multipliers for RSA processors. 416-421
  
• Shai Erez, Guy Even:
  An improved micro-architecture for function approximation using piecewise quadratic interpolation. 422-426
  
• Hani Saleh, Earl E. Swartzlander Jr.:
  A floating-point fused dot-product unit. 427-431
  

Modelling, Estimation and Simulation

• Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran:
  Chip level thermal profile estimation using on-chip temperature sensors. 432-437
  
• Shilpa Bhoj, Dinesh Bhatia:
  Early stage FPGA interconnect leakage power estimation. 438-443
  
• Aswin Sreedhar, Sandip Kundu:
  Modeling and analysis of non-rectangular transistors caused by lithographic distortions. 444-449
  
• Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos:
  A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions. 450-456
  
• Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang:
  Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. 457-462
  

Multi-processor and Multi-core Systems

• Michael Kadin, Sherief Reda:
  Frequency and voltage planning for multi-core processors under thermal constraints. 463-470
  
• Nagesh B. Lakshminarayana, Hyesoon Kim:
  Understanding performance, power and energy behavior in asymmetric multiprocessors. 471-477
  
• Michael Gschwind:
  Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. 478-485
  
• Reza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad:
  The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks. 486-490
  
• Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
  Design and evaluation of an optical CPU-DRAM interconnect. 492-497
  

Emerging Techniques

• Juan Carlos Martinez Santos, Yunsi Fei:
  Leveraging speculative architectures for run-time program validation. 498-505
  
• Michael T. Niemier, Xiaobo Sharon Hu, Aaron Dingler, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod:
  Bridging the gap between nanomagnetic devices and circuits. 506-513
  
• Christopher Nitta, Matthew K. Farrens:
  Techniques for increasing effective data bandwidth. 514-519
  
• Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Kim, Seungryoul Maeng:
  RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache. 520-525
  
• Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
  Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. 526-531
  

Timing

• Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
  Timing analysis considering IR drop waveforms in power gating designs. 532-537
  
• Sz-Cheng Huang, Jie-Hong Roland Jiang:
  A dynamic accuracy-refinement approach to timing-driven technology mapping. 538-543
  
• Veerapaneni Nagbhushan, C. Y. Roger Chen:
  Modeling and reduction of complex timing constraints in high performance digital circuits. 544-550
  
• Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi:
  SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. 551-556
  
• Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
  Is there always performance overhead for regular fabric? 557-562
  

Energy-Efficiency and Security in Processor Designs

• Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot:
  Adaptive techniques for leakage power management in L2 cache peripheral circuits. 563-569
  
• Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte:
  Energy-aware opcode design. 570-576
  
• Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhijie Jerry Shi:
  Making register file resistant to power analysis attacks. 577-582
  
• Shrirang M. Yardi, Michael S. Hsiao:
  Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads. 583-590
  
• Christos Strydis:
  Suitable cache organizations for a novel biomedical implant processor. 591-598
  
• Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera:
  Issue system protection mechanisms. 599-604
  

Low power

• Liang Di, Mateja Putic, John Lach, Benton H. Calhoun:
  Power switch characterization for fine-grained dynamic voltage scaling. 605-611
  
• Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
  A fine-grain dynamic sleep control scheme in MIPS R3000. 612-617
  
• Hao Xu, Ranga Vemuri, Wen-Ben Jone:
  Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. 618-625
  
• Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil:
  Energy-delay tradeoffs in 32-bit static shifter designs. 626-632
  
• Baoxian Zhao, Hakan Aydin, Dakai Zhu:
  Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems. 633-639
  

Tools and Methodologies

• Feng Shi:
  Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits. 640-645
  
• Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin:
  Router and cell library co-development for improving redundant via insertion at pins. 646-651
  
• Nilesh A. Modi, Malgorzata Marek-Sadowska:
  ECO-Map: Technology remapping for post-mask ECO using simulated annealing. 652-657
  
• Dae Hyun Kim, Sung Kyu Lim:
  Global bus route optimization with application to microarchitectural design exploration. 658-663
  
• Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos:
  Fast arbiters for on-chip network switches. 664-670
  

Cache Architectures

• Jason Zebchuk, Srihari Makineni, Donald Newell:
  Re-examining cache replacement policies. 671-678
  
• Chuanjun Zhang, Bing Xue:
  Two dimensional highly associative level-two cache design. 679-684
  
• Chungsoo Lim, Gregory T. Byrd:
  Exploiting producer patterns and L2 cache for timely dependence-based prefetching. 685-692
  
• Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin:
  Ring data location prediction scheme for Non-Uniform Cache Architectures. 693-698
  
• Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum:
  ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. 699-706
  

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