ICCD 2009: Lake Tahoe, CA, USA
27th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009. IEEE 2009 ISBN 978-1-4244-5029-9
Session I
Disruptive Computing Technology
- Nada Amin, William Thies, Saman P. Amarasinghe: Computer-aided design for microfluidic chips based on multilayer soft lithography. 2-9
- Naohiko Shimizu: Reincarnate historic systems on FPGA with novel design methodology. 10-15
Advances in Timing Analysis and Optimization
- Yang Xu, Ken S. Stevens: Automatic synthesis of computation interference constraints for relative timing verification. 16-22
- Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng: Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. 23-28
- Aswin Sreedhar, Sandip Kundu: Statistical timing analysis based on simulation of lithographic process. 29-34
System Power and Thermal Issues
- Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: Compiler-directed leakage reduction in embedded microprocessors. 35-40
- Youngwoo Ahn, Inchoon Yeo, Riccardo Bettati: Efficient calibration of thermal models based on application behavior. 41-46
- Kyungtae Han, Zhen Fang, Paul Diefenbaugh, Richard Forand, Ravi R. Iyer, Donald Newell: Using checksum to reduce power consumption of display systems for low-motion content. 47-53
Session II
Keynote Series: Disruptive Computing Design
- Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren D. Patel, Martin Schoeberl: A disruptive computer design idea: Architectures with repeatable timing. 54-59
- Uzi Vishkin: Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on? 60-63
Hierarchical Testing and Design for Test
- Amit Nahar, Kenneth M. Butler, John M. Carulli Jr., Charles Weinberger: Quality improvement and cost reduction using statistical outlier methods. 64-69
- Brandon Noia, Krishnendu Chakrabarty, Yuan Xie: Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. 70-77
- Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir: Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. 78-83
- Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks: Design and test strategies for microarchitectural post-fabrication tuning. 84-90
- Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Impact analysis of performance faults in modern microprocessors. 91-96
- Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri: A robust pulsed flip-flop and its use in enhanced scan design. 97-102
Clocking, Synchronization and Interconnect
- Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao: Enabling resonant clock distribution with scaled on-chip magnetic inductors. 103-108
- Jean-Michel Chabloz, Ahmed Hemani: A flexible communication scheme for rationally-related clock frequencies. 109-116
- Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu: VariPipe: Low-overhead variable-clock synchronous pipelines. 117-124
- Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: On-chip bidirectional wiring for heavily pipelined systems using network coding. 131-136
Session III
Energy Efficient Architectures
- Weirong Jiang, Viktor K. Prasanna: Reducing dynamic power dissipation in pipelined forwarding engines. 144-149
- Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López: A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. 150-157
- Nasir Mohyuddin, Kimish Patel, Massoud Pedram: Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors. 166-172
System Level Test and Verification
- Vladimir Uzelac, Aleksandar Milenkovic, Milena Milenkovic, Martin Burtscher: Real-time, unobtrusive, and efficient program execution tracing with stream caches and last stream predictors. 173-178
- Jason D. Lee, Rabi N. Mahapatra, Praveen Bhojwani: A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems. 179-185
- Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction-based debugging of system-on-chips with patterns. 186-192
- Robert A. Thacker, Chris J. Myers, Kevin R. Jones, Scott Little: A new verification method for embedded systems. 193-200
- Rupsa Chakraborty, Dipanwita Roy Chowdhury: A hierarchical approach towards system level static timing verification of SoCs. 201-206
Synthesis and Optimization under Reliability Constraints
- Jongyoon Jung, Taewhan Kim: Timing variation-aware high-level synthesis considering accurate yield computation. 207-212
- Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich: 3D stacked power distribution considering substrate coupling. 225-230
- Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Interconnect performance corners considering crosstalk noise. 231-237
Session IV
High Performance Architecture and Advanced Memory
- Yusuke Tanaka, Hideki Ando: Reducing register file size through instruction pre-execution enhanced by value prediction. 238-245
- Oscar Palomar, Toni Juan, Juan J. Navarro: Reusing cached schedules in an out-of-order processor with in-order issue logic. 246-253
- Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie: 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. 254-259
- Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. 268-274
Memory and Processors
- Javier Lira, Carlos Molina, Antonio González: LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. 275-281
- Jiayuan Meng, Kevin Skadron: Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling. 282-288
- Siddhartha Chhabra, Brian Rogers, Yan Solihin: SHIELDSTRAP: Making secure processors truly secure. 289-296
- Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle: Rapid early-stage microarchitecture design using predictive models. 297-304
- Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su, Xiaoyu Li: Efficient binary translation system with low hardware cost. 305-312
Disruptive Trends in Test and Verification (Invited)
- Ender Yilmaz, Sule Ozev: Defect-based test optimization for analog/RF circuits for near-zero DPPM applications. 313-318
- Abhijit Chatterjee, Donghoon Han, Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Hyun Woo Choi, Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhilash Goyal, Deuk Lee, Madhavan Swaminathan: Iterative built-in testing and tuning of mixed-signal/RF systems. 319-326
- Krishnendu Chakrabarty: Testing bio-chips. 327
- A. Hakan Baba, Kee Sup Kim: Framework for massively parallel testing at wafer and package test. 328-334
- Navid Farazmand, Mehdi Baradaran Tahoori: Online multiple error detection in crossbar nano-architectures. 335-342
Best Paper Session
- Shantanu Gupta, Amin Ansari, Shuguang Feng, Scott A. Mahlke: Adaptive online testing for efficient hard fault detection. 343-349
- Chun-Yi Lee, Niraj K. Jha: FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. 350-357
- Xin Fan, Milos Krstic, Eckhard Grass: Analysis and optimization of pausible clocking based GALS design. 358-365
- Fahad Ahmed, Linda S. Milor: Reliable cache design with detection of gate oxide breakdown using BIST. 366-371
Session V
Logic and Memory Design
- Lawrence Leinweber, Christos A. Papachristou, Francis G. Wolff: Efficient architectures for elliptic curve cryptography processors for RFID. 372-377
- In-Cheol Park, Tae-Hwan Kim: Multiplier-less and table-less linear approximation for square and square-root. 378-383
- Sourabh Khire, Saibal Mukhopadhyay: On improving the algorithmic robustness of a low-power FIR filter. 384-389
- Kristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David Brooks, Gu-Yeon Wei: Empirical performance models for 3T1D memories. 398-403
Application-optimized Systems
- Chun He, Alexandros Papakonstantinou, Deming Chen: A novel SoC architecture on FPGA for ultra fast face detection. 412-418
- Seung Eun Lee, Yong Zhang, Zhen Fang, Sadagopan Srinivasan, Ravi Iyer, Donald Newell: Accelerating mobile augmented reality on a handheld platform. 419-426
Session VI
Novel Approaches to Synthesis and Simulation
- Rance Rodrigues, Aswin Sreedhar, Sandip Kundu: Optical lithography simulation using wavelet transform. 427-432
- Adam B. Kinsman, Nicola Nicolici: Computational bit-width allocation for operations in vector calculus. 433-438
- De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li: Topology-driven cell layout migration with collinear constraints. 439-444
- Tsung-Wei Huang, Tsung-Yi Ho: A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips. 445-450
- Romana Fernandes, Ranga Vemuri: Accurate estimation of vector dependent leakage power in the presence of process variations. 451-458
System Level Influence on Architecture
- Michael J. Anderson, Chuck Tsen, Liang-Kai Wang, Katherine Compton, Michael J. Schulte: Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions. 465-471
- Hyung Beom Jang, Ikroh Yoon, Cheol Hong Kim, Seungwon Shin, Sung Woo Chung: The impact of liquid cooling on 3D multi-core processors. 472-478
- Cor Meenderinck, Ben H. H. Juurlink: Intra-vector SIMD instructions for core specialization. 479-484
- Shakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham: A high throughput FFT processor with no multipliers. 485-490
Low Voltage and Low Power
- Mateja Putic, Liang Di, Benton H. Calhoun, John Lach: Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. 491-497
- Rajesh Garg, Sunil P. Khatri: 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. 498-504
- Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri: A radiation tolerant Phase Locked Loop design for digital electronics. 505-510
- Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri: A PLL design based on a standing wave resonant oscillator. 511-516
- Shahrzad Jalali Mazlouman, Alireza Mahanfar, Bozena Kaminska: Mid-range wireless energy transfer using inductive resonance for wireless sensors. 517-522
- Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun: A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. 523-528
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-19T203413 by the dblp team