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  International Conference on Parallel Processing, ICPP'83, Columbus, Ohio, USA, August 1983. IEEE Computer Society 1983

Session 2A: Multistage Network Performance

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  Laxmi N. Bhuyan, C. W. Lee: An Interference Analysis of Interconnection Networks. 2-9
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  Manoj Kumar, J. Robert Jump: Generalized Delta Networks. 10-18
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  Doug DeGroot: Expanding and Contracting SW-Banyan Networks. 19-24
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  Mehrad Yasrebi, Sanjay R. Deshpande, James C. Browne: A Comparison of Circuit Switching and Packet Switching for Data Transfer in Two Simple Image processing Algorithms. 25-28

Session 2B: Numerical Algorithms I

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  Efstratios Gallopoulos, S. D. McEwan: Numerical Experiments with the Massively parallel Processor. 29-35
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  Loyce M. Adams: An M-Step preconditioned Conjugate Gradient Method for Parallel Computation. 36-43
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  John Van Rosendale: Minimizing Inner Product Data Dependencies in Conjugate Gradient Iteration. 44-46
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  Yoshiyasu Takefuji, Takakazu Kurokawa, Masato Ishizaki, Hideo Aiso: New Matrix Equation Solvers in GF(2) Employing Cramer with Chio Method. 47-50

Session 3A: Multistage Networks

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  Bharat Deep Rathi, Sanjay R. Deshpande, Matthew C. Sejnowski, Don Walker, Roy M. Jenevein, G. Jack Lipovski, James C. Browne: Specification and Implementation of an Integrated Packet Communication Facility for an Array Computer. 51-58
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  Sanjay Dhar, Mark A. Franklin, Donald F. Wann: Timing Control of VLSI Based NlogN and Crossbar Networks. 59-64
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  David C. H. Lee, John Paul Shen: Easily-Testable (N, K) Shuffle/Exchange Networks. 65-70
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  Krishnan Padmanabhan, Duncan H. Lawrie: Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks. 71-75
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  Suresh C. Kothari, S. Lakshmivarahan: A Condition Known to be Sufficient for Rearrangeability of the Benes Class of Interconnection Networks with 2x2 Switches Is Also Necessary. 76-78

Session 3B: Numerical Algorithms II

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  Ming-Yang Chern, Tadao Murata: A Fast Algorithm for Concurrent LU Decomposition and Matrix Inversion. 79-86
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  Qing-Shi Gao, Rong-Quan Wang: Vector Computer for Sparse Matrix Operations. 87-89
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  Ming-Yang Chern, Tadao Murata: Efficient Matrix Multiplications on a Concurrent Data-Loading Array Processor. 90-94
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  Tsutomu Hoshino, Tomonori Shirakawa, Takeshi Kamimura, Takahisa Kageyama, Kiyo Takenouchi, Hidehiko Abe, Satoshi Sekiguchi, Yoshio Oyanagi, Toshio Kawai: Highly Parallel Processor Array "PAX" for Wide Scientific Applications. 95-105

Session 4A: Network Connection Capabilities

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  Doug DeGroot: Partitioning Job Structures for SW-Banyan Networks. 106-113
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  Woei Lin, Chuan-lin Wu: Configuring Computation Tree Topologies on a Distributed Computing System. 114-116
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  Robert R. Seban, Howard Jay Siegel: Performing the Shuffle with the PM2I and Illiac SIMD Interconnection Networks. 117-125
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  A. Yavuz Oruç: A Classification of Cube-Connected Networks with a Simple Control Scheme. 126-131

Session 4B: Special Purpose Systems

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  Terrence W. Pratt, Loyce M. Adams, Piyush Mehrotra, John Van Rosendale, Robert G. Voigt, Merrell L. Patrick: The FEM-2 Design Method. 132-134
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  Shigeo Sugimoto, Kiyoshi Agusa, Koichi Tabata, Yutaka Ohno: A Multi-Microprocessor System for Concurrent LISP. 135-143
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  F. M. Tse: A Multi-Micro System for I/O Intensive Applications. 144-147
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  Arumalla V. Reddi: Pipeline and Parallel Architectures for Computer Communication Systems. 148-150
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  Krish Purswani, Bijan Jabbari: An Interface Message Processor with a Multiprocessing Architecture. 151-153

Session 5A: Node-to-Node Networks

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  Jon G. Kuhl, Sudhakar M. Reddy, P. Raghavan: A Class of Graphs for Processor Interconnection. 154-157
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  Karl W. Doty: Dense Bus Connection Networks. 158-160
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  Daniel A. Reed: A Simulation Study of Multimicrocomputer Networks. 161-163
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  Andrew Wilson, Daniel P. Siewiorek, Zary Segall: Evaluation of Multiprocessor Interconnect Structures with the Cm Testbed. 164-171
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  A. I. Noor, G. S. Hope, O. P. Malik: Slot-Based Multi-Access Protocol for Local Computer Network. 172-174

Session 5B: Non-Numerical Algorithms I

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  Baruch Awerbuch, Tripurari Singh: New Connectivity and MSF Algorithms for Ultracomputer and PRAM. 175-179
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  Yung H. Tsin: Bridge-Connectivity and Biconnectivity Algorithms for Parallel Computer Models. 180-182
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  Ten-Hwang Lai, Sartaj Sahni: Anomalies in Parallel Branch-and-Bound Algorithms. 183-190
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  Joseph Mohan: Experience with Two Parallel Programs Solving the Traveling Salesman Problem. 191-193

Session 6A: Tree Structured Systems

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  Scott Danforth: DOT, A Distributed Operating System Model of a Tree-Structured Multiprocessor. 194-201
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  Peyyun Peggy Li, S. Lennart Johnsson: The Tree Machine: An Evaluation of Strategies for Reducing Program Loading Time. 202-205
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  Svetlana P. Kartashev, Steven I. Kartashev: Optimal Routing Algorithms in Multicomputer Networks Organized as Reconfigurable Binary Trees. 206-213

Session 6B: Non-Numerical Algorithms II

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  Quentin F. Stout: Sorting, Merging, Selecting, and Filtering on Tree and Pyramid Machines. 214-221
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  Ching C. Hsiao, Lawrence Snyder: Omni-sort: A Versatile Data Processing Operation for VLSI. 222-225
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  F. P. Hiner III: Pseudo Associative Linking: A High-Speed Searching Algorithm for Parallel Processors. 226-231

Session 7A: Parallel Programming and Languages

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  Ronald H. Perrott, Danny Crookes, Peter Milligan, W. R. Martin Purdy: Implementation of an Array and Vector Processing Language. 232-239
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  Anthony P. Reeves, John D. Bruner: : A Parallel P-Code for Parallel Pascal and Other High Level Languages. 240-243
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  Nam Sung Woo, Ashok K. Agrawala: The DC1 Flow Schema with the Data/Control-Driven Evaluation. 244-251
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  Yury Litvin: Top-Down Data Flow Programming. 252-254

Session 7B: Images and Speech

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  Ikram E. Abdou: A Pipeline Machine for Image Processing Applications. 255-257
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  Yee-Hong Yang, Tsung-Wei Sze: An Evaluation Study of Six Topologies of Parallel Computer Architectures for Scene Matching. 258-260
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  Stephen L. Stepoway, David L. Wells, Gerald R. Kane: An Architecture for Efficient Generation of Fractal Surfaces. 261-268
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  Samuel M. Goldwasser, R. A. Reynolds: An Architecture for the Real-Time Display and Manipulation of Three-Dimensional Objects. 269-274
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  Edward C. Bronson, Leah H. Jamieson: A Parallel Architecture for Labeling, Segmentation, and Lexical Processing in Speech Understanding. 275-280

Session 8A: Expressing Parallelism

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  Jean-Pierre Finance, M. S. Ouerghi: On the Algebraic Specification of Concurrency and Communication. 281-288
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  Lawrence Snyder: Introduction to the Poker Parallel Programming Environment. 289-292
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  Paolo Mancarella, Franco Turini: A High Level Analysis Tool for Concurrent Programs. 293-302
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  Stephen J. Allan, R. R. Oldehoeft: A Stream Definition for Von Neumann Multiprocessors. 303-306

Session 8B: Database Machines/Signal Processing

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  Ghassan Z. Qadah, Keki B. Irani: A Database Machine for Very Large Relational Databases. 307-314
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  Yang-Chang Hong: Efficient Computing of Relational Join Operations by Means of Specialized Hardware. 315-318
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  Hungwen Li: A VLSI Modular Architecture Methodology for Realtime Signal Processing Applications. 319-324
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  Gerhard Fritsch, W. Kleinoeder, Claus-Uwe Linster, Jens Volkert: EMSY85 : The Erlangen Multi-Processor System for a Broad Spectrum of Applications. 325-330

Session 9A: Data Flow

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  Jack B. Dennis, Guang R. Gao: Maximum Pipelining of Array Operations on Static Data Flow Machine. 331-334
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  Israel Koren, Gabriel M. Silberman: A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach. 335-337
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  Lawrence Y. Ho, Keki B. Irani: An Algorithm for Processor Allocation in a Dataflow Multiprocessing Environment. 338-340
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  William Leler: A Small, High-Speed Dataflow Processor. 341-343
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  Prashant S. Sawkar, Timothy J. Forquer, Richard P. Perry: Programmable Modular Signal Processor : A Data Flow Computer System for Real-Time Signal Processing. 344-349

Session 9B: Simulation/Operating Systems

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  Timothy S. Axelrod, Paul F. Dubois, Peter G. Eltgroth: A Simulation for MIMD Performance Prediction : Application to the S-1 MkIIa Multiprocessor. 350-358
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  Avinash Chandak, James C. Browne: Vectorization of Discrete Event Simulation. 359-361
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  Kang G. Shin, Yann-Hang Lee: Analysis of Backward Error Recovery for Concurrent Processes with Recovery Blocks. 362-366
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  Ian A. Newman, R. P. Stallard, M. C. Woodward: Improved Multiprocessor Garbage Collection Algorithms. 367-368

Session 10A: Models

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  Trevor N. Mudge, Abdel-Rahman H. Tawil: Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images. 369-373
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  Yetung P. Chiang, King-sun Fu: Matching Parallel Algorithm and Architecture. 374-380
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  Bruce P. Lester: Coherent Flow of Information in Parallel Systems. 381-383
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  David Jefferson: Virtual Time. 384-394

Session 10B: Scheduling Resources

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  Ruknet Cezzar, David Klappholz: Process Management Overhead in a Speedup-Oriented MIMD System. 395-403
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  Elizabeth Williams: Assigning Processes to Processors in Distributed Systems. 404-406
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  David Lee Tuomenoksa, Howard Jay Siegel: Preloading Schemes for the PASM Parallel Memory System. 407-415
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  Bharadwaj Jayaraman: Constructing a Parallel Implementation from High-Level Specifications: A Case Study Using Resource Expressions. 416-420

Session 11A: System Performance

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  Alexander Thomasian, Paul F. Bay: Queueing Network Models for Parallel Processing of Task Systems. 421-428
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  Hung-Chang Du, Jean-Loup Baer: On the Performance of Interleaved Memories with Non-Uniform Access Probabilities. 429-436
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  Ibrahim H. Önyüksel, Keki B. Irani: A Markovian Queueing Network Model for Performance Evaluation of Bus-Deficient Multiprocessor Systems. 437-439

Session 11B: VLSI Processor Arrays

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  I. V. Ramakrishnan, Donald S. Fussell, Abraham Silberschatz: On Mapping Homogeneous Graphs on a Linear Array-Processor Model. 440-447
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  Peter R. Cappello, Kenneth Steiglitz: Unifying VLSI Array Designs with Geometric Transformations. 448-457
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  Peter J. Varman, Donald S. Fussell: Design of Robust Systolic Algorithms. 458-460

Session 12A: Computer Architectures

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  Andrew R. Pleszkun, Edward S. Davidson: Structured Memory Access Architecture. 461-471
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  Charles E. McDowell: A Simple Architecture for Low Level Parallelism. 472-477
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  Takanobu Baba, Katsuhiro Yamazaki, Nobuyuki Hashimoto, Hiroyuki Kanai, Kenzo Okuda, Kazuhiko Hashimoto: Hierarchical Micro-Architectures of a Two-Level Microprogrammed Multiprocessor Computer. 478-485

Session 12B: Associative Processing/Distributed Systems

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  J. L. Potter: Alternative Data Structures for Lists in Associative Devices. 486-491
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  Martha E. Steenstrup, Daryl T. Lawton, Charles C. Weems: Determination of the Rotational and Translational Components of a Flow Field Using a Content Addressable Parallel Processor. 492-495
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  Srinivas V. Makam, Cauligi S. Raghavendra: Dynamic Relibility Modeling and Analysis of Computer Networks. 496-502
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  Gruia-Catalin Roman, Robert K. Israel: Functional Specification of Distributed Systems. 503-505

Session 13A: Multiprocessor Systems

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  Wong-Hua Lee, Miroslaw Malek: MOPAC: A Partitionable and Reconfigurable Multicomputer Array. 506-510
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  Hans-Joerg Brundiers, Richard E. Buehrer, Hansmartin Friess, Milan Tadian: The Multiprocessor EMPRESS: A Useful Tool for Studying Parallelization Concepts. 511-513
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  Creve Maples, Daniel Weaver, Douglas Logan, William Rathbun: Performance of a Modular Interactive Data Analysis System (MIDAS). 514-519
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  Nikitas J. Dimopoulos: The Homogeneous Multiprocessor Architecture : Structure and Performance Analysis. 520-523
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  Daniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh: Cedar : A Large Scale Multiprocessor. 524-529

Session 13B: Pipeling

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  Clifford N. Arnold: Vector Optimization on the CYBER 205. 530-536
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  Lionel M. Ni, Kai Hwang: Pipelined Evaluation of First-Order Recurrence Systems. 537-543
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  Wilfried Oed, Otto Lange: The Solution of Linear Recurrence Relations on Pipelined Processors. 544-546
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  John Robert Burger: Data-Stationary Instructions as a Way to Minimize Long Distance Communications in VLSI. 547-553