IESS 2007: Irvine, CA, USA
Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig (Eds.): Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA. Springer 2007 IFIP Advances in Information and Communication Technology ISBN 978-0-387-72257-3
Validation and Verification
- Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten: Requirements and Concepts for Transaction Level Assertion Refinement. 1-14
- Bernhard Rieder, Ingomar Wenzel, Klaus Steinhammer, Peter P. Puschner: Using a Runtime Measurement Device with Measurement-Based WCET Analysis. 15-26
- Pierre Niang, Thierry Grandpierre, Mohamed Akil: Implementing Real-Time Algorithms by using the AAA Prototyping Methodology. 27-36
- Karsten Albers, Frank Bodmann, Frank Slomka: Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities. 37-46
- Henning Zabel, Achim Rettberg, Alexander Krupp: Approach for a Formal Verification of a Bit-serial Pipelined Architecture. 47-56
Automotive Applications
- Razvan Racu, Arne Hamann, Rolf Ernst: Automotive System Optimization using Sensitivity Analysis. 57-70
- Richard Anthony, Achim Rettberg, De-Jiu Chen, Isabell Jahnich, Gerrit de Boer, Cecilia Ekelin: Towards a Dynamically Reconfigurable Automotive Control System Architecture. 71-84
- Christian Wawersich, Michael Stilkerich, Wolfgang Schröder-Preikschat: An OSEK/VDX-based Multi-JVM for Automotive Appliances. 85-96
- Isabell Jahnich, Achim Rettberg: Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems. 97-106
Hardware Synthesis
- Jelena Trajkovic, Daniel Gajski: Automatic Data Path Generation from C code for Custom Processors. 107-120
- Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. 121-134
- Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski: An Interactive Design Environment for C-based High-Level Synthesis. 135-144
- Scott Sirowy, Frank Vahid: Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning. 145-154
- Lars Middendorf, Felix Mühlbauer, Georg Umlauf, Christophe Bobda: Embedded Vertex Shader in FPGA. 155-164
Specification and Partitioning
- Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel: A Hybrid Approach for System-Level Design Evaluation. 165-178
- Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo: Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. 179-192
- Pramod Chandraiah, Rainer Dömer: An Interactive Model Re-Coder for Efficient SoC Specification. 193-206
- Mohamed B. Abdelhalim, A. E. Salama, Serag E.-D. Habib: Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique. 207-220
Design Methodologies
- Edison Pignaton de Freitas, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner, Elias Teodoro Silva Jr., Fabiano Costa Carvalho: Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems. 221-230
Embedded Software
- Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada: Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. 241-254
- Noureddine Chabini, Wayne Wolf: Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. 255-268
- Mark Panahi, Trevor Harmon, Juan A. Colmenares, Shruti Gorappa, Raymond Klefstad: Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems. 269-278
- Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer: Embedded Software Development in a System-Level Design Flow. 289-298
Network on Chip
- Rauf Salimi Khaligh, Martin Radetzki: Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. 313-324
- Klaus Steinhammer, Astrit Ademaj: Hardware Implementation of the Time-Triggered Ethernet Controller. 325-338
- Roman Obermaisser, Hermann Kopetz, Christian El Salloum, Bernhard Huber: Error Containment in the Time-Triggered System-On-a-Chip Architecture. 339-352
Medical Applications
- Leonel Sousa, Moisés Simões Piedade, José A. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas: Generic Architecture Designed for Biomedical Embedded Systems. 353-362
- Dirk Jansen, Nidal Fawaz, Daniel Bau, Marc Durrenberger: A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®). 363-372
Distributed and Network Systems
- Dominik Murr, Felix Mühlbauer, Falko Dressler, Christophe Bobda: Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes. 373-386
- Meik Felser, Rüdiger Kapitza, Jürgen Kleinöder, Wolfgang Schröder-Preikschat: Dynamic Software Update of Resource-Constrained Distributed Embedded Systems. 387-400
- Lucas Francisco Wanner, Augusto Born de Oliveira, Antônio Augusto Fröhlich: Configurable Medium Access Control for Wireless Sensor Networks. 401-410
- Augusto Born de Oliveira, Lucas Francisco Wanner, Pierre Kuonen, Antônio Augusto Fröhlich: Integrating Wireless Sensor Networks and the Grid through POP-C++. 411-420
Panel
- K. H. (Kane) Kim: Modeling of Software-Hardware Complexes. 421
- Nikil Dutt: Modeling of Software-Hardware Complexes. 423-425
- K. H. (Kane) Kim: Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization. 427-430
- Hermann Kopetz: Modeling of Software-Hardware Complexes. 431-432
- Franz-Josef Rammig: Software-Hardware Complexes: Towards Flexible Borders. 433-435
Tutorials
- Flávio Rech Wagner, Luigi Carro: Embedded SW Design Space Exploration and Automation using UML-Based Tools. 437-440
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last updated on 2013-06-18T211851 by the dblp team