Gabriele Saucier, Jacques Trilhe (Eds.):
Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992.
IFIP Transactions A-22 North-Holland 1993, ISBN 0-444-81479-5 
@proceedings{DBLP:conf/ifip10-2/1992,
editor = {Gabriele Saucier and
Jacques Trilhe},
title = {Synthesis for Control Dominated Circuits, Selected papers from
the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and
September, 1992},
booktitle = {Synthesis for Control Dominated Circuits},
publisher = {North-Holland},
series = {IFIP Transactions},
volume = {A-22},
year = {1993},
isbn = {0-444-81479-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Chapter 1:
FSM Synthesis
- ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff:
RTL Controller Synthesis.
3-17
- Steve C.-Y. Huang, Wayne Wolf:
Timing-Driven State Assignment for Controller-Datapath Systems.
19-31
- Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala:
Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs.
33-46
- L. Gerbaux, Régis Leveugle, Gabriele Saucier:
Synthesis of large controllers using ROM or PLA generators.
47-59
- Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man:
Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.
61-71
- James Pardey:
The Synthesis of a Parallel Controller from a Petri Net Model.
73-89
- H. Belhadj, L. Gerbaux, Marie-Claude Bertrand, Gabriele Saucier:
Specification and Synthesis of Communicating Finite State Machines.
91-102
- Jochen Beister, Ralf Wollowski:
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior.
103-115
Chapter 2:
Data-path
- Amnon Baron Cohen, Michael Shechory:
Pathway: A datapath layout assembler.
119-131
- Lotfi Ben Ammar, Alain Greiner:
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout.
133-151
- Régis Leveugle, C. Safina:
Generation of optimized datapaths: bit-slice versus standard cells.
153-166
- Evagelos Katsadas, Zohair Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man:
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks.
167-181
- Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura:
Design of data-path module generators from algorithmic representations.
183-192
- Farhad Mavaddat:
Data-Path Synthesis as Grammar Inference.
193-205
Chapter 3:
RTL Synthesis
- E. T. Kapuya, M. D. Edwards:
Microarchitecture/Microcode Synthesis from VHDL.
209-218
- I. Park, Kevin O'Brien, Ahmed Amine Jerraya:
AMICAL: Architectural Synthesis based on VHDL.
219-234
- Yang Wu, Ian Dorrington:
RTL OptimizA: From Control Data Flow Graph to Logic Circuit.
235-247
- Peter Marwedel:
Implementations of IF-statements in the TODOS microarchitecture synthesis system.
249-262
- J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer:
Data Part Optimizations in the CALLAS Synthesis Environment.
263-274
- Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier:
ASYL: A Control Driven RTL Synthesis System using Library Blocks.
275-291
- C. Safina, Régis Leveugle:
Clocking scheme selection for circuits made up of a controller and a datapath.
293-308
Chapter 4:
Module generation
- Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio:
Optimization strategies in symbolic compaction.
311-322
- H. Zhang, Kunihiro Asada:
A general and efficient mask pattern generator for non-series-parallel CMOS transistor network.
323-333
- Pierre Abouzeid, Régis Leveugle, Gabriele Saucier:
Logic Synthesis for Automatic Layout.
335-343
- Eric Gautrin, Laurent Perraudeau:
MADMACS: an environment for the layout of regular arrays.
345-358
- J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven:
Module Generation in an Architectural Synthesis Environment.
359-371
- Andreas Münzner:
BADGE - A synthesis tool for customized arithmetic building blocks.
373-384
- A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson:
Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays.
385-398
- A. J. W. M. ten Berg:
Floorplan Optimized Topological Partitioning of Programmed Logic Arrays.
399-411
- Antonio Martinez:
Timing Model Accuracy Issues and Automated Library Characterization.
413-426
- B. Conq, R. Etienne, T. Perez-Segovia:
Design Library Portability: A Case Study.
427-436
Invited paper
Copyright © Sat Nov 21 00:16:20 2009
by Michael Ley (ley@uni-trier.de)
