VLSI 1999:
Lisbon, Portugal
L. Miguel Silveira, Srinivas Devadas, Ricardo Augusto da Luz Reis (Eds.):
VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal.
IFIP Conference Proceedings 162 Kluwer 2000, ISBN 0-7923-7731-1 
- Shenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail:
Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application.
1-10
- G. B. Jackson, S. V. Awsare, L. D. Engh, M. A. Hemming, P. Holzmann, O. C. Kao, C. Mai-Liu, C. R. Palmer, A. Raina:
An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices.
11-22
- Bingxin Li, Hannu Tenhunen:
A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process.
23-34
- Yue Wu, Shenggao Li, Mohammed Ismail, Håkan Olsson:
A Lower Power CMOS Micromixer for GHz Wireless Applications.
35-46
- S. S. Rajput, S. S. Jamuar:
High Current, Low Voltage Current Mirrors and Applications.
47-60
- Yue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail, Håkan Olsson:
Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications.
61-68
- Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini:
A Fast Parametric Model for Contact-Substrate Coupling.
69-76
- Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie:
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture.
77-88
- A. M. Rassau, G. Alagoda, David Lucas, J. Austin-Crowe, Kamran Eshraghian:
Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications.
89-100
- Camille Diou, Lionel Torres, Michel Robert:
Implementation of a Wavelet Transform Architecture for Image Processing.
101-112
- Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx:
Scalable Run Time Reconfigurable Architecture.
113-124
- Russell Tessier:
Frontier: A Fast Placement System for FPGAs.
125-136
- Nuno Lau, Valery Sklyarov:
Dynamically Reconfigurable Implementation of Control Circuits.
137-148
- R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
An IEEE Compliant Floating Point MAF.
149-160
- C. Ninos, Haridimos T. Vergos, Dimitris Nikolos:
Design and Analysis of On-Chip CPU Pipelined Caches.
161-172
- João M. S. Alcântara, Sergio C. Salomão, Edson do Prado Granja, Vladimir Castro Alves, Felipe M. G. França:
Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation.
173-180
- Rui L. Aguiar, Dinis M. Santos:
Clock Distribution Strategy for IP-based Development.
181-191
- David H. Albonesi:
An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures.
192-205
- Mihai Munteanu, Peter A. Ivey, N. Luke Seed, Marios Psilogeorgopoulos, Neil Powell, Istvan Bogdan:
Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL.
206-218
- Abdoul Rjoub, Odysseas G. Koufopavlou:
Multithreshold Voltage Technology for Low Power Bus Architecture.
219-232
- Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José C. Monteiro:
Integrating Dynamic Power Management in the Design Flow.
233-244
- Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer:
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI.
245-256
- José T. de Sousa:
On Defect-Level Estimation and the Clustering Effect.
257-268
- J. Soares Augusto, C. F. Beltrá Almeida:
FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits.
269-280
- Raimund Ubar, Dominique Borrione:
Design Error Diagnosis in Digital Circuits without Error Model.
281-292
- Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick:
Efficient RLC Macromodels for Digital IC Interconnect.
293-304
- Alex Doboli, Ranga Vemuri:
A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications.
305-317
- Adrián Núñez-Aldana, Ranga Vemuri:
A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements.
318-32
- Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne:
RF Interface Design Using Mixed-Mode Methodology.
326-333
- Rolf Drechsler, Wolfgang Günther:
History-Based Dynamic Minimization During BDD Construction.
334-345
- Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
346-361
- Joonyoung Kim, João P. Marques Silva, Karem A. Sakallah:
Satisfiability-Based Functional Delay Fault Testing.
362-372
- Tomohiro Yoneda:
Verification of Abstracted Instruction Cache of TITAC2: A Case Study.
373-384
- Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita:
Speeding Up Look-up-Table Driven Logic Simulation.
385-397
- Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar:
Efficient Verification of Behavioral Models Using Sequential Sampling Technique.
398-406
- S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres:
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
407-414
- Fernando Moraes, Michel Robert, Daniel Auvergne:
A Virtual CMOS Library Approach for East Layout Synthesis.
415-426
- Ananth Durbha, Srinivas Katkoori:
RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.
427-438
- Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis:
Designing a Mask Programmable Matrix for Sequential Circuits.
439-446
- Stefan Thomas Obenaus, Ted H. Szymanski:
Placements Benchmarks for 3-D VLSI.
447-455
- Edoardo Charbon, Joel R. Phillips:
Substrate Noise: Analysis, Models, and Optimization.
456-472
- Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau:
Architectural Transformations for Hierarchical Algorithmic Descriptions.
473-484
- João M. P. Cardoso, Horácio C. Neto:
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.
485-496
- Flávio Rech Wagner, Márcio Oyamada, Luigi Carro, Márcio Eduardo Kreutz:
Object-Oriented Modeling and Co-Simulation of Embedded Systems.
497-508
- Christophe Jégo, Emmanuel Casseau, Eric Martin:
Architectural Synthesis with Interconnection Cost Control.
509-520
- R. Lerch, M. Kaltenbacher, H. Landes:
CAE Environment for Electromechanical Microsystems.
521-532
- Rainer Brück, Andreas Priebe, Kai Hahn:
Cost Consideration for Application Specific Microsystems Physical Design Stages - A New Approach for Microtechnological Process Design.
533-543
- K. Liateni, D. Moulinier, B. Affour, A. Delpoux, Jean-Michel Karam:
Moving MEMS into Mainstream Applications: The MEMSCAP Solution.
544-556
- Joel R. Phillips, Dan Feng:
Trends in RF Simulation Algorithms.
557-568
- Franz Sischka:
Device Modeling and Measurement for RF Systems.
569-582
- Alexandro M. S. Adário, Sergio Bampi:
Reconfigurable Computing: Viable Applications and Trends.
583-594
- James C. Hoe, Arvind:
Hardware Synthesis from Term Rewriting Systems.
595-619
- Maria-Cristina V. Marinescu, Martin C. Rinard:
A Synthesis Algorithm for Modular Design of Pipelined Circuits.
620-635
- B. F. Romanowicz, M. H. Zaman, S. F. Bart, V. L. Rabinovich, I. Tchertkov, C. Hsu, John R. Gilbert:
A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS.
636-648
- Martin G. Walker, Keh-Jeng Chang, Christophe J. Bianchi:
SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?
649-658
- Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
659-670
Last update Mon May 20 23:45:36 2013
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