VLSI-SOC 2001:
Montpellier, France
Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes (Eds.):
SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France.
IFIP Conference Proceedings 218 Kluwer 2002, ISBN 1-4020-7148-5 
Architecture for Signal & Image Processing
Dynamically Re-configurable Architectures
- Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
51-62
- Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy:
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
63-74
- Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou:
Reconfigurable Architecture Using High Speed FPGA.
75-86
CAD Tools
- Raul Camposano, Don MacMillen:
Design Technology for Systems-on-Chip.
87-96
- Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework.
97-108
- Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa:
High Performance Java Hardware Engine and Software Kernel for Embedded Systems.
109-120
- João Cláudio Soares Otero, Flávio Rech Wagner:
An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures.
121-132
- David Bernard, Christian Landrault, Pascal Nouet:
Interconnect Capacitance Modelling in a VDSM CMOS Technology.
133-144
IP Design & Reuse
High Level Design Methodologies
Power Issues
Design for Specific Constraints
Architectures
Low Power, Low Voltage
Timing Issues
Advance in Mixed Signal
Verification & Validation
Test
- Erik Jan Marinissen:
An Industrial Approach to Core-Based System Chip Testing.
389-400
- Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme.
401-412
- René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST.
413-424
- Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
425-436
- Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski:
Built-in Test of Analog Non-Linear Circuits in a SOC Environment.
437-448
Sensors
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