15. IOLTS 2009: Sesimbra-Lisbon, Portugal

Aging Monitoring and Analysis

• Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann:
  Aging analysis of circuit timing considering NBTI and HCI. 3-8
  
• Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
  Built-in aging monitoring for safety-critical applications. 9-14
  
• C. Guardiani, A. Shibkov, Angelo Brambilla, Giancarlo Storti Gajani, Davide Appello, F. Piazza, Paolo Bernardi:
  An I-IP based approach for the monitoring of NBTI effects in SoCs. 15-20
  
• Elie Maricau, Georges G. E. Gielen:
  A methodology for measuring transistor ageing effects towards accurate reliability simulation. 21-26
  

Transient Faults Evaluation and Analysis

• Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
  Comparing transient-fault effects on synchronous and on asynchronous circuits. 29-34
  
• Carmela Noro Grando, Carlos Arthur Lang Lisbôa, Álvaro Freitas Moreira, Luigi Carro:
  Invariant checkers: An efficient low cost technique for run-time transient errors detection. 35-40
  
• Paolo Maistri, Régis Leveugle:
  Towards automated fault pruning with Petri Nets. 41-46
  

System-Level Reliability and Security

• Massimo Violante, M. L. Esposti:
  A low-cost solution for developing reliable Linux-based space computers for on-board data handling. 49-54
  
• Eberhard Böhl, Paul Duplys:
  Nonlinear compression functions using the MISR approach for security purposes in automotive applications. 55-60
  
• Caroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, Marcos Herve:
  Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults. 61-66
  

Microprocessors and Multiprocessors

• Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Davide Appello:
  Evaluating Alpha-induced soft errors in embedded microprocessors. 69-74
  
• Eleftherios Kolonis, Michael Nicolaidis, Dimitris Gizopoulos, Mihalis Psarakis, Jacques Henri Collet, Piotr Zajac:
  Enhanced self-configurability and yield in multicore grids. 75-80
  
• Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González:
  Online error detection and correction of erratic bits in register files. 81-86
  

Soft Errors and FPGAs

• Niccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet:
  Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. 89-94
  
• Michelangelo Grosso, Matteo Sonza Reorda:
  Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores. 95-100
  
• José Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt:
  Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs. 101-106
  

Memories SEU Tolerance and Characterization

• Antonin Bougerol, Florent Miller, Nadine Buard:
  Novel DRAM mitigation technique. 109-113
  
• Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou:
  SRAM cell design using tri-state devices for SEU protection. 114-119
  
• Sebastiàn A. Bota, Gabriel Torrens, Bartomeu Alorda:
  Critical charge characterization in 6-T SRAMs during read mode. 120-125
  

Panel: Realistic Low Power Design: Let Errors Occur and Correct them Later or Mitigate Errors via Design Guardbanding and Process Control?

• Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Chris Papachristou:
  Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. 129
  

Soft Errors Tolerance

• Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro:
  A fast error correction technique for matrix multiplication algorithms. 133-137
  
• Pedro Reviriego, Juan Antonio Maestro, Anne O'Donnell, Chris J. Bleakley:
  Soft error detection and correction for FFT based convolution using different block lengths. 138-143
  
• Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena:
  In-depth analysis of digital circuits against soft errors for selective hardening. 144-149
  

Design for Reliability and Dependability Issues in Massively Parallel Processor Chips

• Xavier Vera:
  DFx for massively multiprocessors. 153
  
• Vikas Chandra:
  Designing dependable multicore system with unreliable components. 154
  
• Gilles Bizot, Nacer-Eddine Zergainoh, Michael Nicolaidis:
  Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip. 155
  

Coding Techniques

• Michael Richter, Michael Gössel:
  Concurrent checking with split-parity codes. 159-163
  
• Zhen Wang, Mark G. Karpovsky, Berk Sunar:
  Multilinear codes for robust error detection. 164-169
  
• Shih-Hsin Hu, Jacob A. Abraham:
  Error detection in 2-D Discrete Wavelet lifting transforms. 170-175
  

High Altitude and Remote SEU Experiments

• Dan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schäfer, Cyrille Beltrando:
  Highs and lows of radiation testing. 179
  
• Guillaume Hubert, Raoul Velazco, Paul Peronnard:
  A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations. 180
  
• André V. Fidalgo, Gustavo R. Alves, Manuel C. Felgueiras, Manuel G. Gericota:
  Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAs. 181
  

Posters

• Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena:
  Briefing power/reliability optimization in embedded software design. 185-186
  
• Paul Duplys, Eberhard Böhl:
  Linear and nonlinear MISR operations for safety and security in automotive applications. 187-188
  
• Junfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede:
  FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags. 189-191
  
• Salvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano:
  Error detection in addition chain based ECC Point Multiplication. 192-194
  
• Jose Luis Garcia-Gervacio, Víctor H. Champac:
  Detectability analysis of small delays due to resistive opens considering process variations. 195-197
  
• Jose Rocha, Nuno Dias, Angelo Monteiro, Alexandre Neves, Gabriel Santos, Marcelino B. Santos, João Paulo Teixeira:
  Controllability and observability in mixed signal cores. 198-200
  
• Abbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache:
  A fault tolerant journalized stack processor architecture. 201-202
  
• Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena:
  Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. 203-205
  
• Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis:
  An Input Vector Monitoring Concurrent BIST scheme exploiting . 206-207
  
• Pablo Maqueda, Josep Rius:
  Analysis of the extra delay on interconnects caused by resistive opens and shorts. 208-209
  
• Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
  C-testable S-box implementation for secure advanced encryption standard. 210-211
  
• Ashkan Eghbal, Pooria M. Yaghini, Hossein Pedram, Hamid R. Zarandi:
  Fault injection-based evaluation of a synchronous NoC router. 212-214
  

Fault-Tolerance Techniques

• Alireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali:
  A low-cost fault-tolerant technique for Carry Look-Ahead adder. 217-222
  
• Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
  Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. 223-228
  
• Samary Baranov, Ilya Levin, Osnat Keren, Mark G. Karpovsky:
  Designing fault tolerant FSM by nano-PLA. 229-234
  

Field Testing and Self-Adaptation

• Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji:
  Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. 237-242
  
• Kenneth M. Zick, John P. Hayes:
  On-line characterization and reconfiguration for single event upset variations. 243-248
  
• Jayaram Natarajan, Gokul Kumar, Shreyas Sen, Muhammad Mudassar Nisar, Deuk Lee, Abhijit Chatterjee:
  Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levels. 249-254
  

Encoders, Checkers and Fault Secureness

• Houssein Jaber, Fabrice Monteiro, Abbas Dandache:
  An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders. 257-261
  
• Steffen Zeidler, Marcus Ehrig, Milos Krstic, Michael Augustin, Christoph Wolf, Rolf Kraemer:
  Ultra low cost asynchronous handshake checker. 262-268
  
• Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker:
  ATPG-based grading of strong fault-secureness. 269-274
  

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