16. IOLTS 2010: Corfu, Greece
16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July, 2010, Corfu, Greece. IEEE 2010 ISBN 978-1-4244-7724-1
Georgios Karakonstantis, Charles Augustine, Kaushik Roy: A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. 3-8
Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira: Predictive error detection by on-line aging monitoring. 9-14
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara: Aging test strategy and adaptive test scheduling for SoC failure prediction. 21-26
Paolo Rech, Michelangelo Grosso, Fabio Melchiori, D. Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda: Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. 29-34
Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis: Evaluating transient-fault effects on traditional C-element's implementations. 35-40
Sreenivas Gangadhar, Spyros Tragoudas: Probabilistic methods for the impact of an SET in combinational logic. 41-46
Olivier Héron, Julien Guilhemsang, Nicolas Ventroux, Alain Giulieri: Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologies. 49-55
Etienne Faure, Mounir Benabdenbi, François Pêcheux: Distributed online software monitoring of manycore architectures. 56-61
Andreas Merentitis, D. Margaris, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos: SBST for on-line detection of hard faults in multiprocessor applications under energy constraints. 62-67
Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, Yiorgos Makris: An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits. 71-76
Shyam Kumar Devarakond, Shreyas Sen, Aritra Banerjee, Vishwanath Natarajan, Abhijit Chatterjee: Built-in performance monitoring of mixed-signal/RF front ends using real-time parameter estimation. 77-82
Michael G. Dimopoulos, Alexios Spyronasios, Alkis A. Hatzopoulos: Wavelet analysis of measurements for on-line testing analog & mixed-signal circuits. 83-87
Salvatore Campagna, Massimo Violante: A framework to support the design of COTS-based reliable space computers for on-board data handling. 91-96
Long Wang, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Arun Iyengar: Checkpointing virtual machines against transient errors. 97-102
Michel Pignol, Florence Malou, Corinne Aicardi: Qualification and relifing testing for space applications applied to the agilent G-Link components. 103-108
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi: Configurable serial fault-tolerant link for communication in 3D integrated systems. 115-120
Claudia Rusu, Lorena Anghel, Dimiter Avresky: RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip. 121-126
Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue: An FPGA-based fail-soft system with adaptive reconfiguration. 127-132
Josep Altet, Diego Mateo, Eduardo Aldrete-Vidrio: Thermal coupling in ICs: Applications to the test and characterization of analogue and RF circuits. 135
Tiago R. Balen, Marcelo Lubaszewski: Radiation effects on programmable analog devices and mitigation techniques. 136
A. Richardson: Concepts for fault tolerant sensor systems. 137
Sebastiàn A. Bota, Gabriel Torrens, Bartomeu Alorda, J. Verd, Jaume Segura: Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. 141-146
Samuel Evain, Yannick Bonhomme, Valentin Gherman: Programmable restricted SEC codes to mask permanent faults in semiconductor memories. 147-153
Nicholas Axelos, Kiamal Z. Pekmestzi: A bit level area aware cache-based architecture for memory repairs. 154-158
George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos: A software-based self-test methodology for in-system testing of processor cache tag arrays. 159-164
Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena: An on-line fault detection technique based on embedded debug features. 167-172
Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi: A partitioning approach to improve reconfigurable neuron-inspired online BIST. 173-178
Irith Pomeranz, Sudhakar M. Reddy: Selecting state variables for improved on-line testability through output response comparison of identical circuits. 179-184
Josep Rius: A method for detecting resistive opens in buses. 187-189
Niccolò Battezzati, Davide Serrone, Massimo Violante: A new framework for the automatic insertion of mitigation structures in circuits netlists. 190-191
Martin Rozkovec, Jiri Jenícek, Ondrej Novák: Application dependent FPGA testing method using compressed deterministic test vectors. 192-193
Zhen Zhang, Alain Greiner, Mounir Benabdenbi: Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components. 194-196
Piotr Gawkowski, Tomasz Rutkowski, Janusz Sosnowski: Improving fault handling software techniques. 197-199
Raul Chipana, Leticia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, Paulo J. Teixeira: Investigating the Use of BICS to detect resistive-open defects in SRAMs. 200-201
Vitaly Ocheretny: Self-checking arithmetic logic unit with duplicated outputs. 202-203
Navid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori: Online fault testing of reversible logic using dual rail coding. 204-205
Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu: Reconfigurable low-power Concurrent Error Detection in logic circuits. 206-207
Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena: Robust cryptographic ciphers with on-line statistical properties validation. 208-210
David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia: Trustworthy computing in a multi-core system using distributed scheduling. 211-213
Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal: 3D integration: Circuit design, test, and reliability challenges. 217
Michael Nicolaidis, Vladimir Pasca, Lorena Anghel: Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems. 218
Yervant Zorian: Test and reliability concerns for 3D-ICs. 219
K. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Evaluation of concurrent error detection techniques on the advanced encryption standard. 223-228
Paul Duplys, Eberhard Böhl, Wolfgang Rosenstiel: Key randomization using a power analysis resistant deterministic random bit generator. 229-234
Michel Agoyan, Jean-Max Dutertre, Amir-Pasha Mirbaha, David Naccache, Anne-Lise Ribotta, Assia Tria: How to flip a bit? 235-239
Zhen Wang, Mark G. Karpovsky: Robust FSMs for cryptographic devices resilient to strong fault injection attacks. 240-245
Michael N. Skoufis, Spyros Tragoudas: On-line detection of random voltage perturbations in buses with multiple-threshold receivers. 249-254
Steffen Tarnick: Design of embedded constant weight code checkers based on averaging operations. 255-260
Steffen Zeidler, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer: On-line testing of bundled-data asynchronous handshake protocols. 261-267
Michael Augustin, Michael Gössel, Rolf Kraemer: Reducing the area overhead of TMR-systems by protecting specific signals. 268-273
V. Prasanth, Virendra Singh, Rubin A. Parekhji: Robust detection of soft errors using delayed capture methodology. 277-282
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni: Timing error tolerance in nanometer ICs. 283-288
Joshua W. Wells, Jayaram Natarajan, Abhijit Chatterjee: Error resilient video encoding using Block-Frame Checksums. 289-294



