9. ISCA 1982:
Austin, TX, USA
Stephen A. Szygenda, John Hughes, Matt Blanton, Terry J. Wagner, Dennis J. Frailey, Tom Gunter, Chuck McLeavy, G. Jack Lipovski, Miroslaw Malek (Eds.):
9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982.
IEEE Computer Society 1982
- David A. Patterson, Richard S. Piepho:
RISC assessment: A high-level language experiment.
3-8

- Douglas W. Clark, Henry M. Levy:
Measurement and analysis of instruction use in the VAX-11/780.
9-17

- Krishna M. Kavi, Boumediene Belkhouche, Evelyn Bullard, Lois M. L. Delcambre, Stephen M. Nemecek:
HLL architectures: Pitfalls and predilections.
18-23

- Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir:
The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine (Extended Abstract).
27-42

- King-Hang Chu, King-Sun Fu:
VLSI architectures for high speed recognition of context-free languages and finite-state languages.
43-49

- Mark A. Franklin, Donald F. Wann:
Asynchronous and clocked control structures for VLSI based interconnection networks.
50-59

- Robert J. McMillen, Howard Jay Siegel:
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network.
63-72

- D. S. Parker, C. S. Raghavendra:
The Gamma network: A multiprocessor interconnection network with redundant paths.
73-80

- Roy M. Jenevein, James C. Browne:
A control processor for a reconfigurable array computer.
81-89

- Laxmi N. Bhuyan, Dharma P. Agrawal:
A general class of processor interconnection strategies.
90-98

- Forbes J. Burkowski:
Instruction set design issues relating to a static dataflow computer.
101-111

- James E. Smith:
Decoupled access/execute computer architectures.
112-119

- L. J. Caluwaerts, J. Debacker, J. A. Peperstraete:
A data flow architecture with a paged memory system.
120-127

- B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard:
Efficient code generation for horizontal architectures: Compiler techniques and architectural support.
131-139

- Gene C. Barton:
Sentry: A novel hardware implementation of classic operating system mechanisms.
140-147

- Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon:
A logic simulation machine.
148-157

- Subrata Dasgupta, Marius Olafsson:
Towards a family of languages for the design and implementation of machine architectures.
158-167

- Woei Lin, Chuan-lin Wu:
Design of a 2 × 2 fault-tolerant switching element.
181-189

- Donald S. Fussell, Peter J. Varman:
Fault-tolerant wafer-scale architectures for VLSI.
190-198

- Sakti Pramanik:
Database filters.
201-210

- Mario Tokoro, Takashi Takizuka:
On the semantic structure of information - A proposal of the abstract storage architecture.
211-217

- Yasunori Dohi, Akira Suzuki, Noriyuki Matsui:
Hardware sorter and its application to data base machine.
218-225

- Philip C. Treleaven, Richard P. Hopkins:
A recursive computer architecture for VLSI.
229-238

- M. Castan, Elliott I. Organick:
µ3L: An HLL-RISC processor for parallel execution of FP-language programs.
239-247

- Ferdinand Hommes:
The heap/substitution concept - an implementation of functional operations on data structures for a reduction machine.
248-256

- Paul F. Reynolds Jr.:
A shared resource algorithm for distributed simulation.
259-266

- Bijendra N. Jain:
Duplication of packets and their detection in X.25 communication protocols.
267-273

- Pauline Markenscoff:
A multiple processor system for real time control tasks.
274-280

- Leslie Jill Miller:
A heterogeneous multiprocessor design and the distributed scheduling of its task group workload.
283-290

- George H. Goble, Michael H. Marsh:
A dual processor VAX 11/780.
291-298

- Michel Dubois, Faye A. Briggs:
Effects of cache coherency in multiprocessors.
299-308

- Trevor N. Mudge, B. A. Makrucki:
Probabilistic analysis of a crossbar switch.
311-320

- Steven P. Levitan, Caxton C. Foster:
Finding an extremum in a network.
321-325

- U. V. Premkumar, James C. Browne:
Resource allocation in rectangular SW banyans.
326-333

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