27. ISCA 2000: Vancouver, BC, Canada

• J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry:
  A scalable approach to thread-level speculation. 1-12
  
• Marcelo H. Cintra, José F. Martínez, Josep Torrellas:
  Architectural support for scalable speculative parallelization in shared-memory multiprocessors. 13-24
  
• Steven K. Reinhardt, Shubhendu S. Mukherjee:
  Transient fault detection via simultaneous multithreading. 25-36
  
• Quinn Jacobson, James E. Smith:
  Trace preconstruction. 37-46
  
• Ryan Rakvic, Bryan Black, John Paul Shen:
  Completion time multiple branch prediction for enhancing trace cache performance. 47-58
  
• Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu:
  A hardware mechanism for dynamic extraction and relayout of program hot spots. 59-70
  
• Mark Oskin, Frederic T. Chong, Matthew K. Farrens:
  HLS: combining statistical and symbolic simulation to guide microprocessor designs. 71-82
  
• David Brooks, Vivek Tiwari, Margaret Martonosi:
  Wattch: a framework for architectural-level power analysis and optimizations. 83-94
  
• Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye:
  Energy-driven integrated hardware-software optimizations using SimplePower. 95-106
  
• Erik G. Hallnor, Steven K. Reinhardt:
  A fully associative software-managed cache design. 107-116
  
• Ashley Saulsbury, Fredrik Dahlgren, Per Stenström:
  Recency-based TLB preloading. 117-127
  
• Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens:
  Memory access scheduling. 128-138
  
• An-Chow Lai, Babak Falsafi:
  Selective, accurate, and timely self-invalidation using last-touch prediction. 139-148
  
• Norman Margolus:
  An embedded DRAM architecture for large-scale spatial-lattice computations. 149-160
  
• Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz:
  Smart Memories: a modular reconfigurable architecture. 161-171
  
• Craig B. Zilles, Gurindar S. Sohi:
  Understanding the backward slices of performance degrading instructions. 172-181
  
• Kevin M. Lepak, Mikko H. Lipasti:
  On the value locality of store instructions. 182-191
  
• Zarka Cvetanovic, Richard E. Kessler:
  Performance analysis of the Alpha 21264-based Compaq ES40 system. 192-202
  
• Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, Fred Homewood:
  Lx: a technology platform for customizable VLIW embedded processing. 203-213
  
• Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi:
  Reconfigurable caches and their application to media processing. 214-224
  
• Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee:
  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. 225-235
  
• Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami:
  Circuits for wide-window superscalar processors. 236-247
  
• Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger:
  Clock rate versus IPC: the end of the road for conventional microarchitectures. 248-259
  
• James E. Smith, Greg Faanes, Rabin A. Sugumar:
  Vector instruction set support for conditional operations. 260-269
  
• Yuan C. Chou, John Paul Shen:
  Instruction path coprocessors. 270-281
  
• Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese:
  Piranha: a scalable architecture based on single-chip multiprocessing. 282-293
  
• Ramesh Radhakrishnan, Deependra Talla, Lizy Kurian John:
  Allowing for ILP in an embedded Java processor. 294-305
  
• Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen:
  Early load address resolution via register tracking. 306-315
  
• José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham:
  Multiple-banked register file architectures. 316-325
  

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