29. ISCA 2002: Anchorage, Alaska, USA

Yale N. Patt, Dirk Grunwald, Kevin Skadron (Eds.): 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA. IEEE Computer Society 2002, ISBN 0-7695-1605-X

Processor Pipelines

Allan Hartstein, Thomas R. Puzak:
The Optimum Pipeline Depth for a Microprocessor. 7-13
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. 14-24
Eric Sprangle, Doug Carmean:
Increasing Processor Performance by Implementing Deeper Pipelines. 25-

Processor Scheduling

Dan Ernst, Todd M. Austin:
Efficient Dynamic Scheduling Through Tag Elimination. 37-46
Brian A. Fields, Rastislav Bodík, Mark D. Hill:
Slack: Maximizing Performance Under Technological Constraints. 47-58
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan:
A Large, Fast Instruction Window for Tolerating Cache Misses. 59-70
Ho-Seop Kim, James E. Smith:
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. 71-

Safety and Reliability

T. N. Vijaykumar, Irith Pomeranz, Karl Cheng:
Transient-Fault Recovery Using Simultaneous Multithreading. 87-98
Shubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt:
Detailed Design and Evaluation of Redundant Multithreading Alternatives. 99-110
Milos Prvulovic, Josep Torrellas, Zheng Zhang:
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. 111-122
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood:
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. 123-

Power Aware Architecture

Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. 137-147
Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge:
Drowsy Caches: Simple Techniques for Reducing Leakage Power. 148-157
Anoop Iyer, Diana Marculescu:
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. 158-

Memory Systems

Yan Solihin, Josep Torrellas, Jaejin Lee:
Using a User-Level Memory Thread for Correlation Prefetching. 171-182
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black:
Avoiding Initialization Misses to the Heap. 183-194
Gokul B. Kandiraju, Anand Sivasubramaniam:
Going the Distance for TLB Prefetching: An Application-Driven Study. 195-

Dynamic Optimization

Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras:
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. 209-220
Ilhyun Kim, Mikko H. Lipasti:
Implementing Optimizations at Decode Time. 221-232
Ashutosh S. Dhodapkar, James E. Smith:
Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. 233-

Data and Storage Networks

Philip Buonadonna, David E. Culler:
Queue Pair IP: A Hybrid Architecture for System Area Networks. 247-256
Yuanyuan Zhou, Kai Li, Angelos Bilas, Suresh Jagannathan, Cezary Dubnicki, James Philbin:
Experiences with VI Communication for Database Storage. 257-

Vector Architectures

Alex Pajuelo, Antonio González, Mateo Valero:
Speculative Dynamic Vectorization. 271-280
Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec:
Tarantula: A Vector Extension to the Alpha Architecture. 281-

Supporting Deep Speculatio

André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. 295-306
Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz:
Difficult-Path Branch Prediction Using Subordinate Microthreads. 307-317
Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt:
A Scalable Instruction Queue Design Using Dependence Chains. 318-

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