36. ISCA 2009:
Austin, TX, USA Stephen W. Keckler, Luiz André Barroso (Eds.):
36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA.
ACM 2009, ISBN 978-1-60558-526-0
New memory technology
- Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger:
Architecting phase change memory as a scalable dram alternative.
- Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang:
A durable and energy efficient main memory using phase change memory technology.
- Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers:
Scalable high performance main memory system using phase-change memory technology.
- Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie:
Hybrid cache architecture with disparate memory technologies.
Prefetching and streaming
Reliability and fault tolerance
Multimedia and mobile
- Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner:
AnySP: anytime anywhere anyway signal processing.
- John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
Rigel: an architecture and scalable programming interface for a 1000-core accelerator.
- Sunpyo Hong, Hyesoon Kim:
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness.
Load and stores
DRAM and SSD
- Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu:
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.
- Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch:
Disaggregated memory for expansion and sharing in blade servers.
- Cagdas Dirik, Bruce L. Jacob:
The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization.
Power in chip multiprocessors
Hardware support for monitoring and debugging
- Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Trevor N. Mudge:
End-to-end performance forecasting: finding bottlenecks before they happen.
- Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin:
Scaling the bandwidth wall: challenges in and avenues for CMP scaling.
- Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz:
A fault tolerant, area efficient architecture for Shor's factoring algorithm.
Memory system reconfiguration and acceleration
- Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig:
Performance and power of cache-based reconfigurable computing.
- Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
A memory system design framework: creating smart memories.
- José A. Joao, Onur Mutlu, Yale N. Patt:
Flexible reference-counting-based hardware acceleration for garbage collection.
On-chip interconnection networks
- Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary:
Firefly: illuminating future network-on-chip with nanophotonics.
- Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi:
Phastlane: a rapid transit optical routing network.
- Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti:
Achieving predictable performance through better memory controller placement in many-core CMPs.
Speculative threading and parallelization
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- Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas:
Dynamic performance tuning for speculative threads.
- Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
- Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay:
Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.