36. ISCA 2009: Austin, TX, USA

• Katherine A. Yelick:
  Ten ways to waste a parallel computer. 1
  

New memory technology

• Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger:
  Architecting phase change memory as a scalable dram alternative. 2-13
  
• Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang:
  A durable and energy efficient main memory using phase change memory technology. 14-23
  
• Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers:
  Scalable high performance main memory system using phase-change memory technology. 24-33
  
• Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie:
  Hybrid cache architecture with disparate memory technologies. 34-45
  

Real time

• Jinho Suh, Michel Dubois:
  Dynamic MIPS rate stabilization in out-of-order processors. 46-56
  
• Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero:
  Hardware support for WCET analysis of hard real-time multicore systems. 57-68
  

Prefetching and streaming

• Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi:
  Spatio-temporal memory streaming. 69-80
  
• Pedro Diaz, Marcelo Cintra:
  Stream chaining: exploiting multiple levels of correlation in data prefetching. 81-92
  

Reliability and fault tolerance

• Michael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee:
  Architectural core salvaging in a multi-core processor for hard-error tolerance. 93-104
  
• Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González:
  End-to-end register data-flow continuous self-test. 105-115
  
• Doe Hyun Yoon, Mattan Erez:
  Memory mapped ECC: low-cost error protection for last level caches. 116-127
  

Multimedia and mobile

• Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner:
  AnySP: anytime anywhere anyway signal processing. 128-139
  
• John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
  Rigel: an architecture and scalable programming interface for a 1000-core accelerator. 140-151
  
• Sunpyo Hong, Hyesoon Kim:
  An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. 152-163
  

Cache organization

• Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong:
  Multi-execution: multicore caching for data-similar executions. 164-173
  
• Yuejian Xie, Gabriel H. Loh:
  PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. 174-183
  
• Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki:
  Reactive NUCA: near-optimal block placement and replication in distributed caches. 184-195
  

Routing

• Thomas Moscibroda, Onur Mutlu:
  A case for bufferless routing in on-chip networks. 196-207
  
• Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas:
  Application-aware deadlock-free oblivious routing. 208-219
  
• Nan Jiang, John Kim, William J. Dally:
  Indirect adaptive routing on large scale interconnection networks. 220-231
  
• James R. Hamilton:
  Internet-scale service infrastructure efficiency. 232
  

Load and stores

• Colin Blundell, Milo M. K. Martin, Thomas F. Wenisch:
  InvisiFence: performance-transparent memory ordering in conventional multiprocessors. 233-244
  
• Andrew D. Hilton, Amir Roth:
  Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. 245-254
  

DRAM and SSD

• Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu:
  Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. 255-266
  
• Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch:
  Disaggregated memory for expansion and sharing in blade servers. 267-278
  
• Cagdas Dirik, Bruce L. Jacob:
  The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. 279-289
  

Power in chip multiprocessors

• Abhishek Bhattacharjee, Margaret Martonosi:
  Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. 290-301
  
• Krishna K. Rangan, Gu-Yeon Wei, David Brooks:
  Thread motion: fine-grained power management for multi-core systems. 302-313
  
• Yefu Wang, Kai Ma, Xiaorui Wang:
  Temperature-constrained power control for chip multiprocessors with online model estimation. 314-324
  

Hardware support for monitoring and debugging

• Jie Yu, Satish Narayanasamy:
  A case for an interleaving constrained shared-memory multi-processor. 325-336
  
• Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas:
  SigRace: signature-based data race detection. 337-348
  
• Vijay Nagarajan, Rajiv Gupta:
  ECMon: exposing cache events for monitoring. 349-360
  

Potpourri

• Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Trevor N. Mudge:
  End-to-end performance forecasting: finding bottlenecks before they happen. 361-370
  
• Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin:
  Scaling the bandwidth wall: challenges in and avenues for CMP scaling. 371-382
  
• Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz:
  A fault tolerant, area efficient architecture for Shor's factoring algorithm. 383-394
  

Memory system reconfiguration and acceleration

• Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig:
  Performance and power of cache-based reconfigurable computing. 395-405
  
• Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
  A memory system design framework: creating smart memories. 406-417
  
• José A. Joao, Onur Mutlu, Yale N. Patt:
  Flexible reference-counting-based hardware acceleration for garbage collection. 418-428
  

On-chip interconnection networks

• Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary:
  Firefly: illuminating future network-on-chip with nanophotonics. 429-440
  
• Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi:
  Phastlane: a rapid transit optical routing network. 441-450
  
• Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti:
  Achieving predictable performance through better memory controller placement in many-core CMPs. 451-461
  

Speculative threading and parallelization

• Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas:
  Dynamic performance tuning for speculative threads. 462-473
  
• Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
  Boosting single-thread performance in multi-core systems through fine-grain multi-threading. 474-483
  
• Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay:
  Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. 484-495
  

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