39. ISCA 2012: Portland, OR, USA

Memory Systems I

• Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu:
  RAIDR: Retention-aware intelligent DRAM refresh. 1-12
  
• Mahdi Nazm Bojnordi, Engin Ipek:
  PARDIS: A programmable memory controller for the DDRx interfacing standards. 13-24
  
• Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan:
  BOOM: Enabling mobile memory based low-power server DIMMs. 25-36
  
• Krishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz:
  Towards energy-proportional datacenter memory with mobile DRAM. 37-48
  

GPU Architectures

• Nicolas Brunie, Sylvain Collange, Gregory Frederick Diamos:
  Simultaneous branch and warp interweaving for sustained GPU performance. 49-60
  
• Minsoo Rhu, Mattan Erez:
  CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures. 61-71
  
• Jaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam:
  iGPU: Exception support and speculative execution on GPUs. 72-83
  
• Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis:
  Boosting mobile GPU performance with a decoupled access/execute fragment processor. 84-93
  

Architectures for Security

• Mehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh, Dmitry Ponomarev:
  Branch regulation: Low-overhead protection from code reuse attacks. 94-105
  
• John Demme, Robert Martin, Adam Waksman, Simha Sethumadhavan:
  Side-channel vulnerability factor: A metric for measuring information leakage. 106-117
  
• Robert Martin, John Demme, Simha Sethumadhavan:
  TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks. 118-129
  
• Jonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Dan Shumow, Vinod Vaikuntanathan, Timothy Sherwood:
  Inspection resistant memory: Architectural support for security from physical examination. 130-141
  

Interconnection Networks

• Yi Xu, Jun Yang, Rami G. Melhem:
  Tolerating process variations in nanophotonic on-chip networks. 142-152
  
• Pranay Koka, Michael O. McCracken, Herb Schwetman, Chia-Hsin Owen Chen, Xuezhe Zheng, Ron Ho, Kannan Raj, Ashok V. Krishnamoorthy:
  A micro-architectural analysis of switched photonic multi-chip interconnects. 153-164
  
• Aaron Carpenter, Jianyun Hu, Övünç Kocabas, Michael C. Huang, Hui Wu:
  Enhancing effective throughput for transmission line-based bus. 165-176
  
• Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova:
  A case for random shortcut topologies for HPC interconnects. 177-188
  

Architectures for Software Productivity

• Santosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic:
  Watchdog: Hardware for safe and secure manual memory management and full memory safety. 189-200
  
• Joseph Devietti, Benjamin P. Wood, Karin Strauss, Luis Ceze, Dan Grossman, Shaz Qadeer:
  RADISH: Always-on sound and complete race detection in software and hardware. 201-212
  

Heterogeneity

• Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer:
  Scheduling heterogeneous multi-cores through performance impact estimation (PIE). 213-224
  
• Ting Cao, Stephen M. Blackburn, Tiejun Gao, Kathryn S. McKinley:
  The Yin and Yang of power and performance for asymmetric hardware and managed software. 225-236
  

Circuits and Technology

• Evgeni Krimer, Patrick Chiang, Mattan Erez:
  Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures. 237-248
  
• Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu:
  VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors. 249-260
  

Reliability

• Ioannis Doudalis, Milos Prvulovic:
  Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability. 261-272
  
• Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John:
  A first-order mechanistic model for architectural vulnerability factor. 273-284
  
• Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
  LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. 285-296
  

Cache Systems

• Arkaprava Basu, Mark D. Hill, Michael M. Swift:
  Reducing memory reference energy with opportunistic virtual caching. 297-308
  
• Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez:
  Improving writeback efficiency with decoupled last-write prediction. 309-320
  
• Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim:
  FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. 321-332
  

Dependable Architectures

• Gaurang Upasani, Xavier Vera, Antonio González:
  Setting an error detection infrastructure with low cost acoustic wave detectors. 333-343
  
• Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco:
  Viper: Virtual pipelines for enhanced reliability. 344-355
  
• Olivier Temam:
  A defect-tolerant accelerator for emerging high-performance applications. 356-367
  

Memory Systems II

• Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu:
  A case for exploiting subarray-level parallelism (SALP) in DRAM. 368-379
  
• Moinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis Lastras:
  PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. 380-391
  
• Elliott Cooper-Balis, Paul Rosenfeld, Bruce Jacob:
  Buffer-on-board memory systems. 392-403
  

Scheduling and Resource Management

• Myoungsoo Jung, Ellis Herbert Wilson, Mahmut T. Kandemir:
  Physically Addressed Queueing (PAQ): Improving parallelism in Solid State Disks. 404-415
  
• Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu:
  Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. 416-427
  
• R. Manikantan, Kaushik Rajan, R. Govindarajan:
  Probabilistic Shared Cache Management (PriSM). 428-439
  

Application Analysis

• Nadathur Satish, Changkyu Kim, Jatin Chhugani, Hideki Saito, Rakesh Krishnaiyer, Mikhail Smelyanskiy, Milind Girkar, Pradeep Dubey:
  Can traditional programming bridge the Ninja performance gap for parallel computing applications? 440-451
  
• Melanie Kambadur, Kui Tang, Martha A. Kim:
  Harmony: Collection and analysis of parallel block vectors. 452-463
  

Virtualized Systems

• David Wentzlaff, Christopher J. Jackson, Patrick Griffin, Anant Agarwal:
  Configurable fine-grain protection for multicore processor virtualization. 464-475
  
• Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh:
  Revisiting hardware-assisted page walks for virtualized systems. 476-487
  

Data Centers

• Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing:
  Managing distributed UPS energy for effective power capping in data centers. 488-499
  
• Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Yusuf Onur Koçberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Özer, Babak Falsafi:
  Scale-out processors. 500-511
  
• Chao Li, Amer Qouneh, Tao Li:
  iSwitch: Coordinating and optimizing renewable energy powered server clusters. 512-523
  

HW/SW Interface and Flexibility

• Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd D. Millstein, Madanlal Musuvathi:
  End-to-end sequential consistency. 524-535
  
• Jason Mars, Naveen Kumar:
  BlockChop: Dynamic squash elimination for hybrid processor architecture. 536-547
  
• Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Mattan Erez:
  The dynamic granularity memory system. 548-560
  

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