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Proceedings of the 3rd Annual Symposium on Computer Architecture,
January 1976
- Gordon Bell, William D. Strecker:
Computer Structures: What Have We Learned from the PDP-11?
1-14
- Helmut Kerner, Werner Beyerle:
A PMS Level Language for Performance Evaluation Modelling (V-PMS).
15-19
- M. Moalla, Gabriele Saucier, Joseph Sifakis, M. Zachariades:
A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules.
20-27
- Jonathan Allen:
A Course in Computer Structures.
28-32
- George E. Rossmann:
The IEEE Computer Society Task Force on Computer Architecture.
33
- Lawrence C. Widdoes Jr.:
The Minerva Multi-Micropocessor.
34-39
- R. G. Arnold:
A Hierarchical, Restructurable Multi-Microprocessor Architecture.
40-45
- Robert McGill, John Steinhoff:
A Multimicroprocessor Approach to Numerical Analysis: An Application to Gaming Problems.
46-51
- John E. Jensen, Jean-Loup Baer:
A Model of Interference in a Shared Resource Multiprocessor.
52-57
- C. Leung, David Misunas, A. Neczwid, Jack B. Dennis:
A Computer Simulation Facility for Packet Communication Architecture.
58-63
- S. L. Rege:
Cost, Performance and Size Tradeoffs for Different Levels in a Memory Hierarchy.
64-67
- Paul E. Dworak, Alice C. Parker:
An Input Interface for Real-Time Digital Sound Generation System.
68-73
- Michael C. Mulder, Patrick P. Fasang:
A Microprocessor Oriented Data Acquisition and Control System for Power System Control.
74-78
- H. M. Gladney, Gerd Hochweller:
Multiprogramming for Real-Time Applications.
79-85
- Theodore H. Kehl:
Basil Architecture - An HLL Minicomputer.
86-92
- Harold W. Lawson Jr.:
Function Distribution in Computer System Architectures.
93-97
- Chris A. Vissers:
Interface, A Dispersed Architecture.
98-104
- Alexander Thomasian, Algirdas Avizienis:
A Design Study of a Shared Resource Computing System.
105-112
- Warwick S. Ford, V. Carl Hamacher:
Hardware Support for Inter-Process Communication and Processor Sharing.
113-118
- Ulrich Trambacz, Georg Hyla:
A Taxonomy of Display Processors.
119-120
- Werner E. Kluge:
Traversing Binary Tree Structures with Shift Register Memories.
121
- Eduardo B. Fernández, Rita C. Summers, Charles D. Coleman:
Architecture Support for System Protection.
121
- James W. Gault, Alice C. Parker:
The Design of a User-Programmable Digital Interface.
121
- Philip S. Liu, Frederic J. Mowle:
Selection Schemes for Dynamically Microcoding Fortran Programs.
122
- Serge Fournier, Ming T. Liu:
System Design of a Grammar-Programmable High-Level Language Machine.
122
- Ch. Kuznia, R. Kober, H. Kopp:
SMS 101 - A Structured Multimicroprocessor System with Deadlock-Free Operation Scheme.
122
- Samuel H. Fuller, Daniel P. Siewiorek, R. J. Swan:
The Design of a Multi-Micro-Computer System.
123
- Cecil C. Reames, Ming T. Liu:
Design and Simulation of the Distributed Loop Computer Network (DLCN).
124-129
- Paolo Franchi:
Distribution of Functions and Control in RPCNET.
130-135
- Larry D. Wittie:
Efficient Message Routing in Mega-Micro-Computer Networks.
136-140
- Terry A. Welch:
An Investigation of Descriptor Oriented Architecture.
141-146
- Edward A. Feustel:
Tagged Architecture and the Semantics of Programming Languages: Extensible Types.
147-150
- Alan P. Batson, Robert E. Brundage, John P. Kearns:
Design Data for Algol-60 Machines.
151-154
- William D. Strecker:
Cache Memories for PDP-11 Family Computers.
155-158
- Janak H. Patel, Edward S. Davidson:
Improving the Throughput of a Pipeline by Insertion of Delays.
159-164
- A. M. Abd-Alla, Laird H. Moffett:
On-Line Architecture Tuning Using Microcapture.
165-171
- Leonard D. Healy:
A Character-Oriented Context-Addressed Segment Sequential Storage.
172-177
- J. A. Bush, G. Jack Lipovski, Stanley Y. W. Su, J. K. Watson, S. J. Ackerman:
Some Implementations of Segment Sequential Functions.
178-185
- M. DeMartinis, G. Jack Lipovski, Stanley Y. W. Su, J. K. Watson:
A Self-Managing Secondary Memory System.
186-194
- Samuel H. Fuller:
Price/Performance Comparison of C.mmp and the PDP-10.
195-202
Copyright © Fri Dec 4 20:19:17 2009
by Michael Ley (ley@uni-trier.de)