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Proceedings of the 5th Annual Symposium on Computer Architecture,
April 1978
- Glen S. Miranker:
A Digital Signal Processor for Real Time Generation of Speech Waveforms.
1-7
- Amar Mukhopadhyay:
Hardware Alorithms for Nonnumeric Computation.
8-16
- Alan Huang:
An Optical Residue Arithmetic Unit.
17-23
- Mary Jane Irwin:
A Pipelined Processing Unit for On-Line Division.
24-30
- G. Jack Lipovski:
Architectural Features of CASSM: A Context Addressed Segment Sequential Memory.
31-38
- Lee A. Hollaar:
Rotating Memory Processors for the Matching of Complex Textual Patterns.
39-43
- Krishnamurthi Kannan:
The Design of a Mass Memory for a Database Computer.
44-51
- Stewart A. Schuster, H. B. Nguyen, Esen A. Ozkarahan, Kenneth C. Smith:
RAP.2 - An Associative Processor for Data Bases.
52-59
- H. J. Bürkle, A. Frick, Ch. Schilier:
High Level Language Oriented Hardware and the Post-Von Neumann Era.
60-65
- Peter G. Hibbard, Andy Hisgen, Thomas L. Rodeheffer:
A Language Implementation Design for a Multiprocessor Computer System.
66-72
- Harry J. Saal:
A Hardware Architecture for Controlling Information Flow.
73-77
- Klaus J. Berkling:
Computer Architecture for Correct Programming.
78-84
- Edgar Maymon, Daniel Tabak:
Selection of Microprocessor Equipment.
85-88
- Larry L. Kinney, R. G. Arnold:
Analysis of a Multiprocessor System with a Shared Bus.
89-95
- Rajani M. Kant, Takayuki Kimura:
Decentralized Parallel Algorithms for Matrix Computation.
96-100
- Richard L. Sites:
An Analysis of the Cray-1 Computer.
101-106
- Glenford J. Myers:
Storage Concepts in a Software-Reliabiltiy.
107-113
- Scott E. Woodard, Gernot Metze:
Self-Checking Alternating Logic: Sequential Circuit Design.
114-122
- L. Boi, P. Michel:
An Approach to a Fault-Tolerant System Architecture.
123-130
- K. H. Kim, C. V. Ramamoorthy:
Structure of an Efficient Duplex Memory for Processing Fault-Tolerant Programs.
131-138
- Suhas S. Patil, Terry A. Welch:
An Approach to Using VLSI in Digital Systems.
139-143
- Alvin M. Despain, David A. Patterson:
X-Tree: A Tree Structured Multi-Processor Computer Architecture.
144-151
- Philip E. Stanley:
Address Size Independence in a 16-Bit Minicomputer.
152-158
- Alice C. Parker, Andrew W. Nagle:
Description and Simulation of Microcode Execution.
159-165
- Mario Jino, Jane W.-S. Liu:
Intelligent Magnetic Bubble Memories.
166-174
- Wolfgang K. Giloi, Helmut K. Berg:
Data Structure Architectures - A Major Operational Principle.
175-181
- David J. DeWitt:
DIRECT - A Multiprocessor Organization for Supporting Relational Data Base Management Systems.
182-189
- Robert D. Russell:
The PDP-11: A Case Study of How Not to Design Condition Codes.
190-194
- Hassan K. Reghbati, V. Carl Hamacher:
Hardware Support for the Concurrent Programming in Loosely Coupled Multiprocessors.
195-201
- Faye A. Briggs:
Performance of Memory Configurations for Parallel-Pipelined Computers.
202-209
- A. L. Davis:
The Architecure and System Method of DDM1: A Recursively Structured Data Driven Machine.
210-215
- S. Nishikawa, M. Sato, K. Murakami:
Interconnection Unit for Poly-Processor System: An Analysis and Design.
216-222
- Howard Jay Siegel, S. Diane Smith:
Study of Multistage SIMD Interconnection Networks.
223-229
- Paolo Corsini, Graziano Frosini, Fabrizio Grandoni, G. Galati, M. La Manna:
The Serial Microprocessor Array (SMA): Microprogramming and Application Examples.
230-235
- Daniel Davies:
Reliable Synchronization of Redundant Systems.
236-237
- Donald F. Towsley:
The Effects of CPU: I/O Overlap on Computer System Configurations.
238-241
- Alan Jay Smith:
On the Effectiveness of Buffered and Multiple Arm Disks.
242-248
- Janak H. Patel:
Pipelines wth Internal Buffers.
249-255
Copyright © Wed Nov 11 04:27:13 2009
by Michael Ley (ley@uni-trier.de)