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Proceedings of the 7th Annual Symposium on Computer Architecture,
May 1980
- Jack B. Dennis, G. Andrew Boughton, Clement K. C. Leung:
Building Blocks for Data Flow Prototypes.
1-8
- Edward S. Davidson:
A Multiple Stream Microprocessor Prototype System: AMP-1.
9-16
- F. André, Jean-Pierre Banâtre, H. Leroy, G. Paget, Florimond Ployette, Jean-Paul Routeau:
Kensur: An Architecture Oriented Towards Programming Languages Translation.
17-22
- Jon G. Kuhl, Sudhakar M. Reddy:
Distributed Fault-Tolerance For Large Multiprocessor Systems.
23-30
- Miroslaw Malek:
A Comparison Connection Assignment for Diagnosis of Multiprocessor Systems.
31-36
- Karl-Erwin Großpietsch, Jörg Kaiser, Edgar Nett:
A Concept for Test and Reconfiguration of a Fault-Tolerant VLSI Processor System.
37-43
- Jean-Paul Brassard, Jan Gecsei:
Path Building in Cellular Partitioning Networks.
44-50
- Robert J. McMillen, Howard Jay Siegel:
MIMD Machine Communication Using the Augmented Data Manipulator Network.
51-60
- John Paul Shen, John P. Hayes:
Fault Tolerance of a Class of Connecting Networks.
61-71
- Edward G. Coffman Jr., Kimming So:
On the Comparison Between Single and Multiple Processor Systems.
72-79
- V. Carl Hamacher, Gerald S. Shedler:
Performance of a Collision-Free Local Bus Network Having Asynchronous Distributed Control.
80-87
- Wlodzimierz M. Zuberek:
Timed Petri Nets and Preliminary Performance Evaluation.
88-96
- David R. Ditzel, David A. Patterson:
Retrospective on High-Level Language Computer Architecture.
97-104
- Jean-Paul Sansonnet, Michel Castan, Christian Percebois:
M3L: A List-Directed Architecture.
105-112
- Yasushi Hibino:
A Practical Parallel Garbage Collection Algorithm and Its Implementation.
113-120
- Philip C. Trevleaven, Geoffrey F. Mole:
A Multi-Processor Reduction Machine for User-Defined Reduction Languages.
121-130
- Jeffrey M. Tobias:
A Single User Multiprocessor Incorporating Processor Manipulation Facilities.
131-138
- Robert H. Halstead Jr., Stephen A. Ward:
The Munet: A Scalable Decentralized Architecture For Parallel Computers.
139-145
- Butler W. Lampson, Kenneth A. Pier:
A Processor for a High-Performance Personal Computer.
146-160
- David B. G. Edwards, Alan E. Knowles, J. V. Woods:
MU6-G: A New Design to Achieve Mainframe Performance from a Mini-Sized Computer.
161-167
- Kenneth E. Batcher:
Architecture of a Massively Parallel Processor.
168-173
- John Palmer:
The Intel 8087 Numeric Data Processor.
174-181
- Robert H. Kuhn:
Efficient Mapping of Algorthims To Single-Stage Interconnections.
182-189
- David Nassimi:
A Self-Routing Benes Network.
190-195
- Hermann von Issendorff, W. Grunewald:
An Adaptable Network for Functional Distributed Systems.
196-201
- Mokhtar Boshra Riad:
A Combination of Field and Current Access Techniques for Effiecient and Cost-Effective Bubble Memories.
202-210
- Kishor S. Trivedi:
Designing Linear Storage Hierarchies so as to Maximize Reliability Subject to Cost and Performance Constraints.
211-217
- Sudhir Ahuja, Charles S. Roberts:
An Associative/Parallel Processor for Partial Match Retrieval Using Superimposed Codes.
218-227
- M. D. Ruggiero, Safwat G. Zaky:
A Microprocessor-Based Virtual Memory System.
228-235
- Anand Jagannathan:
A Technique for the Architectural Implementation of Software Subsystems.
236-244
- Viktors Berstis:
Security and Protection of Data in the IBM System/38.
245-252
- Miguel Garcia Hoffman:
Hardware Implementation of Communication Protocols: A Formal Approach.
253-263
- P. Guillier, D. Slosberg:
An Architecture with Comprehensive Facilities of Inter-Process Synchronization and Communication.
264-270
- Robert M. Lougheed, David L. McCubbrey:
The Cytocomputer: A Practical Pipelined Image Processor.
271-277
- Constantine Halatsis, Andries van Dam, J. Joosten, M. Letheren:
Architectural Considerations for a Microprogrammable Emulating Engine Using Bitslices.
278-291
- Mary Jane Irwin, Don Heller:
Online Pipeline Systems for Recursive Numeric Computations.
292-299
- M. J. Foster, H. T. Kung:
Design of Special-Purpose VLSI Chips: Example and Opinions.
300-307
- Anshul Kumar, P. C. P. Bhatt:
A Structured Language for CAD of Digital Systems.
308-316
- Uwe Hercksen, Rainer Klar, Wolfgang Kleinöder:
Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA.
317-324
- Mario Tokoro, Klichiro Tamaru, Masaaki Mizuno, Masao Hori:
A High-Level Multi-Lingual Multiprocessor KMP.
325-333
Copyright © Fri Nov 27 19:41:27 2009
by Michael Ley (ley@uni-trier.de)