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Proceedings of the 8th Annual Symposium on Computer Architecture,
May 1981
- Arvind:
Data Flow Languages and Architecture.
1
- Kenneth J. Thurber:
A Pragmatic View of Distributed Processing Systems.
1
- Bruce W. Arden, Ran Ginosar:
MP/C: A Multiprocessor/Computer Architecture.
3-20
- Dharma P. Agrawal:
A Pipelined Pseudoparallel System Architecture for Motion Analysis.
21-36
- Richard F. Hobson:
Structured Machine Design: An Ongoing Experiement.
37-56
- Roy M. Jenevein, Doug DeGroot, G. Jack Lipovski:
A Hardware Support Mechanism for Scheduling Resources in a Parallel Machine Environment.
57-66
- Faye A. Briggs, Michel Dubois, Kai Hwang:
Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS.
67-80
- David Kroft:
Lockup-Free Instruction Fetch/Prefetch Cache Organization.
81-88
- Wei C. Yen, King-sun Fu:
Analysis of Multiprocessor Cache Organizations with Alternative Main Memory Update Policies.
89-106
- W. L. Bain Jr., S. R. Ahuja:
Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems.
107-134
- James E. Smith:
A Study of Branch Prediction Strategies.
135-148
- Arpad Gallo, Richard P. Wilder:
Performance Measurement of Data Communication Systems with Emphasis on Open System Interconnections (OSI).
149-162
- G. W. Geitz, E. J. Schmitter:
BFS-Realization of a Fault-Tolerant Architecuture.
163-170
- Mamoru Maekawa:
Optimal Processor Interconnection Topologies.
171-186
- Michel Dubois, Faye A. Briggs:
Efficient Interprocessor Communications for MIMD Multiprocessor Systems.
187-196
- Bryan D. Ackland, Neil Weste, David J. Burr:
An Integrated Multiprocessing Array for Time Warp Pattern Matching.
197-216
- Norton Greenfeld:
Jericho: A Professional's Personal Computer System.
217-226
- Bruce W. Arden, Ran Ginosar:
A Single-Relation Module for a Data Base Machine.
227-238
- Benjamin W. Wah, Y. W. Eva Ma:
MANIP - A Parallel Computer System for Implementing Branch and Bound Algorithms.
239-262
- P. I. Georgiadis, Mike P. Papazoglou, D. G. Maritsas:
Towards a Parallel SIMULA Machine.
263-278
- Philip C. Treleaven, Richard P. Hopkins:
Decentralized Computation.
279-290
- Arvind V. Kathail:
A Multiprocessor Data Flow Machine that Supports Generalized Procedures.
291-302
- Vason P. Srini:
An Architecture for Extended Abstract Data Flow.
303-326
- Forbes J. Burkowski:
A Multi-User Data Flow Architecture.
327-340
- M. E. Houdek, F. G. Soltis, R. L. Hoffman:
IBM System/38 Support for Capability-Based Addressing.
341-348
- P. Xia, X. Fang, Y. Wang, G. Wang, Y. Liu, C. Li, C. Lin, W. Zhan, Q. Sun:
An Array Processor for Petroleum Exploration.
349-354
- K. E. MacKenzie:
On Refuting the Creation Theory of Computer Architecture.
355
- James E. Thornton:
Heterogeneous Computer Architecture.
355-356
- Robert J. Souza, Edward E. Balkovich:
Impact of Hardware Interconnection Structures on the Performance of Decentralized Software.
357-366
- Makoto Hasegawa, Tadao Nakamura, Yoshiharu Shigei:
Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging.
367-372
- Sudhir K. Arora, Surya R. Dumpala, K. C. Smith:
WCRC: An ANSI SPARC Machine Architecture for Data Base Management.
373-388
- Kazuo Seo, A. Minematsu, Hideo Aiso, Noriyuki Kamibayashi:
A Look-Ahead Data Staging Architecture for Relational Data Base Machines.
389-406
- Yasushi Kiyoki, Katsumi Tanaka, Hideo Aiso, Noriyuki Kamibayashi:
Design and Evaluation of a Relational Data Base Machine Employing Advanced Data Structures and Algorithms.
407-424
- Israel Koren:
A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array.
425-442
- David A. Patterson, Carlo H. Séquin:
RISC I: A Reduced Instruction Set VLSI Computer.
443-458
- Larry L. Kinney, W. Y. Yueh, Walter L. Heimerdinger, Richard R. Ramseyer, J. W. Thomas:
An Architecture for a VHSIC Computer.
459-470
- Carlo H. Séquin:
Doubly Twisted Torus Networks for VLSI Processing Arrays.
471-480
- Wolfgang K. Giloi, Peter M. Behr:
An IPC Protocol and Its Hardware Realization for a High-Speed Distributed Multicomputer System.
481-494
- Z. Chuang-qi, S. Ren-Ben:
Alignment Network Used for Connecting a Prime Number of Memory Blocks with a Power of 2 of Processing Elements.
495-500
- Roger M. Needham:
Design Considerations for a Processing Server.
501-504
- Robert J. McMillen, Howard Jay Siegel:
Dynamic Rerouting Tag Schemes for the Augmented Data Manipulator Network.
505-516
Copyright © Tue Dec 1 16:20:41 2009
by Michael Ley (ley@uni-trier.de)