11. ISCA 1984:
Ann Arbor,
USA
Proceedings of the 11th Annual Symposium on Computer Architecture,
June 1984,
Ann Arbor,
USA
- Forbes J. Burkowski:
A Vector and Array Multiprocessor Extension of the Sylvan Architecture.
4-11
- Alejandro A. Kapauan, J. Timothy Field, Dennis Gannon, Lawrence Snyder:
The Pringle Parallel Computer.
12-20
- Mehrad Yasrebi, G. Jack Lipovski:
A State-of-the-Art SIMD Two-Dimensional FFT Array Processor.
21-27
- Y.-W. Ma, R. Krishnamurti:
The Architecture of REPLICA-A Special-Purpose Computer System for Active Multi-Sensory Perception of 3-Dimensional Objects.
30-37
- Samuel M. Goldwasser:
A Generalized Object Display Processor Architecture.
38-47
- Katsura Kawakami, Shigeo Shimazaki:
A Special Purpose LSI Processor Using the DDA Algorithm for Image Transformation.
48-54
- Benjamin W. Wah, Guo-Jie Li, Chee Fen Yu:
The Status of MANIP-A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems.
56-63
- Rubén González-Rubio, J. Rohmer, D. Terral:
The Schuss Filter: A Processor for Non-Numerical Data Processing.
64-73
- Carl Ebeling, Andrew J. Palay:
The Design and Implementation of a VLSI Chess Move Generator.
74-80
- Manjai Lee, Chuan-lin Wu:
Performance Analysis of Circuit Switching Baseline Interconnection Networks.
82-90
- Clyde P. Kruskal, Marc Snir:
The Importance of Being Square.
91-98
- Chi-Yuan Chin, Kai Hwang:
Connection Principles for Multipath Packet Switching Networks.
99-108
- Shlomo Weiss, James E. Smith:
Instruction Issue Logic for Pipelined Supercomputers.
110-118
- Robert G. Wedig, Marc A. Rose:
The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow.
119-125
- Utpal Banerjee, Daniel Gajski:
Fast Execution of Loops With IF Statements.
126-132
- Daniel Gajski, Won Kim, Shinya Fushimi:
A Parallel Pipelined Relational Query Processor: An Architectural Overview.
134-141
- Arun K. Somani, Vinod K. Agarwal:
An Efficient VLSI Dictionary Machine.
142-150
- Allan L. Fisher:
Dictionary Machines With a Small Number of Processors.
151-156
- Mark D. Hill, Alan Jay Smith:
Experimental Evaluation of On-Chip Microprocessor Cache Memories.
158-166
- James R. Goodman, MenChow Chiang:
The Use of Static Column RAM as a Memory Hierarchy.
167-174
- Yutaka Ishikawa, Mario Tokoro:
The Design of an Object Oriented Architecture.
178-187
- David Ungar, Ricki Blau, Peter Foley, A. Dain Samples, David A. Patterson:
Architecture of SOAR: Smalltalk on a RISC.
188-197
- Pradip Bose, Edward S. Davidson:
Design of Instruction Set Architectures for Support of High-Level Languages .
198-206
- Patrice Quinton:
Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations.
208-214
- Chang Nian Zhang, David Y. Y. Yun:
Multi-Dimensional Systolic Networks for Discrete Fourier Transform.
215-222
- José A. B. Fortes, Dan I. Moldovan:
Data Broadcasting in Linearly Scheduled Array Processors.
224-231
- I. V. Ramakrishnan, Peter J. Varman:
Modular Matrix Multiplication on a Linear Array.
232-238
- T. R. N. Rao:
Joint Encryption and Error Correction Schemes.
240-241
- Bella Bose:
Unidirectional Error Correction/Detection for VLSI Memory.
242-244
- C. L. Chen:
Error-Correcting Codes for Semiconductor Memories.
245-247
- Khaled A. S. Abdel-Ghaffar, Robert J. McEliece:
Soft Error Correction for Increased Densities in VLSI Memories.
248-250
- Richard M. King, Robert A. Wagner:
Combining Speed with Alpha-Particle Induced Memory Error Tolerance in a Large Boolean Vector Machine (Extended Abstract).
251-253
- Laxmi N. Bhuyan:
On the Performance of Loosely Coupled Multiprocessors.
256-262
- Ravi Mehrotra, Sarosh Talukdar:
Scheduling of Tasks for Distributed Processors.
263-270
- Krishna M. Kavi, Edward W. Banios:
Message Repository Definitional Facility: An Architectural Model for Interprocess Communication.
271-278
- Prithviraj Banerjee, Jacob A. Abraham:
Fault-Secure Algorithms for Multiple-Processor Systems.
279-287
- Lubomir Bic:
Execution of Logic Programs on a Dataflow Architecture.
290-296
- Walter G. Rudd, Duncan A. Buell, Donald M. Chiarulli:
A High Performance Factoring Machine.
297-300
- Joel S. Emer, Douglas W. Clark:
A Characterization of Processor Performance in the VAX-11/780.
301-310
- Wolf-Dietrich Moeller, Gerd Sandweg:
The Peripheral Processor PP4 - A Highly Regular VLSI Processor.
312-318
- Lars Philipson:
VLSI Based Design Principles for MIMD Multiprocessor Computers with Distributed Memory Management.
319-327
- Maheswara R. Samatham:
Dhiraj K. Pradhan: A Multiprocessor Network Suitable for Single-Chip VLSI Implementation.
328-337
- Larry Rudolph, Zary Segall:
Dynamic Decentralized Cache Schemes for MIMD Parallel Processors.
340-347
- Mark S. Papamarcos, Janak H. Patel:
A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories.
348-354
- James K. Archibald, Jean-Loup Baer:
An Economical Solution to the Cache Coherence Problem.
355-362
- Ilkka J. Haikala:
Cache Hit Ratios With Geometric Task Switch Intervals.
364-371
Copyright © Sat Nov 28 22:18:31 2009
by Michael Ley (ley@uni-trier.de)
