13. ISCA 1986: Tokyo, Japan

• Haruo Yokota, Hidenori Itoh:
  A Model and an Architecture for a Relational Knowledge Base. 2-9
  
• Makoto Amamiya, Masaru Takesue, Ryuzo Hasegawa, Hirohide Mikami:
  Implementation and Evaluation of a List-Processing-Oriented Data Flow Machine. 10-19
  
• K. Takahashi, H. Yamada, H. Nagai, K. Matsumi:
  A New String Search Hardware Architecture for VLSI. 20-27
  
• Anoop Gupta, Charles Forgy, Allen Newell, Robert G. Wedig:
  Parallel Algorithms and Architectures for Rule-Based Systems. 28-37
  
• Robert H. Halstead Jr., Thomas L. Anderson, Randy B. Osborne, Thomas L. Sterling:
  Concert: Design of a Multiprocessor Development System. 40-48
  
• H. T. Kung:
  Memory Requirements for Balanced Computer Architectures. 49-54
  
• Yang-Chang Hong, Thomas H. Payne, Le Baron O. Ferguson:
  Graph Allocation in Static Dataflow Systems. 55-64
  
• Prathima Agrawal, Rakesh Agrawal:
  Software Implementation of a Recursive Fault Tolerance Algorithm on a Network of Computers. 65-72
  
• Tohru Nojiri, Shumpei Kawasaki, Kousuke Sakoda:
  Microprogrammable Processor for Object-Oriented Architecture. 74-81
  
• Shreekant S. Thakkar, William E. Hostmann:
  An Instruction Fetch Unit for a Graph Reduction Machine. 82-91
  
• Edward F. Gehringer, Robert P. Colwell:
  Fast Object-Oriented Procedure Calls: Lessons from the Intel 432. 92-101
  
• Daniel M. Dias, Balakrishna R. Iyer, Philip S. Yu:
  On Coupling Many Small Systems for Transaction Processing. 104-110
  
• Mohammad Malkawi, Janak H. Patel:
  Performance Measurement of Paging Behavior in Multiprogramming Systems. 111-118
  
• Anant Agarwal, Richard L. Sites, Mark Horowitz:
  ATUM: A New Technique for Capturing Address Traces Using Microcode. 119-127
  
• Michael J. Wise:
  Experimenting With EPILOG: Some Results and Preliminary Conclusions. 130-139
  
• Yasuro Shobatake, Hideo Aiso:
  A Unification Processor Based on a Uniformly Structured Cellular Hardware. 140-148
  
• Noriyoshi Ito, Masatoshi Sato, Eiji Kuno, Kazuaki Rokusawa:
  The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D. 149-156
  
• André Seznec:
  An Efficient Routing Control Unit for the SIGMA Network E(4). 158-168
  
• Jean-Daniel Nicoud, K. Skala:
  REYSM, A High Performance, Low Power Multi-Microprocessor Bus. 169-174
  
• Kyungsook Y. Lee, Wael Hegazy:
  The Extra Stage Gamma Network. 175-182
  
• Masanobu Yuhara, Akira Hattori, Masashi Niwa, Mitsuhiro Kishimoto, Hiromu Hayashi:
  Evaluation of the FACOM ALPHA Lisp Machine. 184-190
  
• Andrew R. Pleszkun, Matthew Thazhuthaveetil:
  An Architecture for Efficient Lisp List Access. 191-198
  
• Toshiyuki Nakata, Nobuhiko Koike:
  A Functional Level Simulation Engine of MAN-YO: A Special Purpose Parallel Machine for Logic Design Automation. 202-208
  
• Edward H. Frank:
  Exploiting Parallelism in a Switch-Level Simulation Machine. 209-215
  
• Thomas S. Anantharaman, Roberto Bisiani:
  A Hardware Accelerator for Speech Recognition Algorithms. 216-223
  
• Toshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi:
  Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations. 226-234
  
• John Sargeant, Chris C. Kirkham:
  Stored Data Structures on the Manchester Dataflow Machine. 235-242
  
• K. Kawakami, John R. Gurd:
  A Salable Dataflow Structure Store. 243-250
  
• Makoto Hasegawa, Yoshiharu Shigei:
  AT2=O(N log4 N), T=O(log N) Fast Fourier Transform in a Light Connected 3-Dimensional VLSI. 252-260
  
• Krzysztof Sapiecha, R. Jarocki:
  Modular Architecture for High Performance Implementation of FFT Algorithm. 261-270
  
• Juan J. Navarro, José M. Llabería, Mateo Valero:
  Computing Size-Independent Matrix Problems on Systolic Array Processors. 271-278
  
• Shinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara:
  A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines. 280-289
  
• Masaharu Hirayama:
  VLSI Oriented Asynchronous Architecture. 290-296
  
• Wen-mei W. Hwu, Yale N. Patt:
  HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. 297-306
  
• Kenji Onaga, Takahiro Takechi:
  On Design of Rotary Array Communication and Wavefront-Driven Algorithms for Solving Large-Scale Band-Limited Matrix Equations. 308-315
  
• Leonard M. Napolitano Jr.:
  A Computer Architecture for Dynamic Finite Element Analysis. 316-323
  
• David T. Harper III, J. Robert Jump:
  Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme. 324-328
  
• Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima:
  Pseudo MIMD Array Processor - AAP2. 330-337
  
• Allan L. Fisher:
  Scan Line Array Processors for Image Computation. 338-345
  
• Marco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb:
  Warp Architecture and Implementation. 346-356
  
• David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson:
  An In-Cache Address Translation Mechanism. 358-365
  
• David R. Cheriton, Gert Slavenburg, Patrick D. Boyle:
  Software-Controlled Caches in the VMP Multiprocessor. 366-374
  
• James R. Goodman, Wei-Chung Hsu:
  On the Use of Registers vs. Cache to Minimize Memory Traffic. 375-383
  
• Peter Y.-T. Hsu, Edward S. Davidson:
  Highly Concurrent Scalar Processing. 386-395
  
• Scott McFarling, John L. Hennessy:
  Reducing the Cost of Branches. 396-403
  
• Steven R. Kunkel, James E. Smith:
  Optimal Pipelining in Supercomputers. 404-411
  
• Paul Sweazey, Alan Jay Smith:
  A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. 414-423
  
• Philip Bitar, Alvin M. Despain:
  Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. 424-433
  
• Michel Dubois, Christoph Scheurich, Faye A. Briggs:
  Memory Access Buffering in Multiprocessors. 434-442
  
• George S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn:
  Evaluation of the SPUR Lisp Architecture. 444-452
  

Last update Thu May 23 02:02:07 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page