16. ISCA 1989:
Jerusalem, Israel
Jean-Claude Syre (Ed.):
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989.
ACM 1989, ISBN 0-89791-319-1
- Susan J. Eggers, Randy H. Katz:
Evaluating the Performance of Four Snooping Cache Coherency Protocols.
2-15

- David R. Cheriton, Hendrik A. Goosen, Patrick D. Boyle:
Multi-level Shared Caching Techniques for Scalability in VMP-M/C.
16-24

- Atsuhiro Goto, Akira Matsumoto, Evan Tick:
Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures.
25-33

- V. Gerald Grafe, G. S. Davidson, Jamie E. Hoch, V. P. Holmes:
The Epsilon Dataflow Processor.
36-45

- Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba:
An Architecture of a Dataflow Single Chip Processor.
46-53

- Peter Nitezki:
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine.
54-61

- Roland N. Ibbett, T. M. Hopkins, K. I. M. McKinnon:
Architectural Mechanisms to Support Sparse Vector Processing.
64-71

- David T. Harper III, Darel A. Linebarger:
A Dynamic Storage Scheme for Conflict-Free Vector Access.
72-77

- Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita:
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.
78-85

- Yosi Ben-Asher, David Egozi, Assaf Schuster:
2-D SIMD Algorithms in the Perfect Shuffle Networks.
88-95

- Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Systematic Hardware Adaptation of Systolic Algorithms.
96-104

- Ming-Syan Chen, Kang G. Shin:
Task Migration in Hypercube Multiprocessors.
105-111

- Steven A. Przybylski, Mark Horowitz, John L. Hennessy:
Characteristics of Performance-Optimal Multi-Level Cache Hierarchies.
114-121

- David A. Wood, Randy H. Katz:
Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache.
122-130

- Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill:
Inexpensive Implementations of Set-Associativity.
131-139

- Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy:
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy.
140-148

- Chris R. Jesshope, P. R. Miller, Jay T. Yantchev:
High Performance Communications in Processor Networks.
150-157

- Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan:
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks.
158-166

- Steven L. Scott, Gurindar S. Sohi:
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks.
167-176

- Paul D. Ezhilchelvan, Santosh K. Shrivastava, Alan Tully:
Constructing Replicated Systems Using Processors with Point-to-Point Communication Links.
177-184

- Hans Benker, Jean-Michel Beacco, Sylvie Bescos, Michel Dorochevsky, Thomas Jeffré, Anita Pohlmann, Jacques Noyé, Bruno Poterie, Alan P. Sexton, Jean-Claude Syre, Oliver Thibault, Günter Watzlawik:
KCM: A Knowledge Crunching Machine.
186-194

- Ashok Singhal, Yale N. Patt:
A High Performance Prolog Processor with Multiple Function Units.
195-202

- M. Morioka:
S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP.
203-210

- Kam-Fai Wong, M. Howard Williams:
A Type Driven Hardware Engine for Prolog Clause Retrieval over a Large Knowledge Base.
211-222

- Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang:
Comparing Software and Hardware Schemes For Reducing the Cost of Branches.
224-233

- Matthew K. Farrens, Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches.
234-241

- Wen-mei W. Hwu, Pohua P. Chang:
Achieving High Instruction Cache Performance with an Optimizing Compiler.
242-251

- Peter Steenkiste:
The Impact of Code Density on Instruction Cache Performance.
252-259

- Rishiyur S. Nikhil:
Can Dataflow Subsume von Neumann Computing?
262-272

- Wolf-Dietrich Weber, Anoop Gupta:
Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results.
273-280

- Norman P. Jouppi:
Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU.
281-289

- Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto:
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
290-297

- Andy Hopper, Alan Jones, Dimitris Lioupis:
Multiple vs. Wide Shared Bus Multiprocessors.
300-306

- Marco Annaratone, Roland Rühl:
Performance Measurements on a Commercial Multiprocessor Running Parallel Code.
307-314

- Marco Annaratone, Claude Pommerell, Roland Rühl:
Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors.
315-324

- Dipak Ghosal, Satish K. Tripathi, Laxmi N. Bhuyan, Hong Jiang:
Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures.
325-333

- Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
Logic Simulation on Massively Parallel Architectures.
336-343

- Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh:
R256: A Research Parallel Processor for Scientific Computation.
344-351

- Manuel L. Anido, D. J. Allerton, Ed Zaluska:
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine.
354-361

- J. M. Mulder, R. J. Portier, A. Srivastava, R. in 't Velt:
An Architecture Framework for Application-Specific and Scalable Architectures.
362-369

- Kichul Kim, Viktor K. Prasanna:
Perfect Latin Squares and Parallel Array Access.
372-379

- Shlomo Weiss:
An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors.
380-386

- Chuen-Liang Chen, Chung-Kai Liao:
Analysis of Vector Access Performance on Skewed Interleaved Memory.
387-394

- Anant Agarwal, Mathews Cherian:
Adaptive Backoff Synchronization Techniques.
396-406

- Per Stenström:
A Cache Consistency Protocol for Multiprocessors with Multistage Networks.
407-415

- Hong-Men Su, Pen-Chung Yew:
On Data Synchronization for Multiprocessors.
416-423

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