18. ISCA 1991: Toronto, Canada

• Ronald F. DeMara, Dan I. Moldovan:
  The SNAP-1 Parallel AI Prototype. 2-11
  
• Wei Siong Tan, H. Russ, Cecil O. Alford:
  GT-EP: A Novel High-Performance Real-Time Architecture. 13-21
  
• Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu:
  IXM2: A Parallel Associative Processor. 22-31
  
• David R. Kaeli, Philip G. Emma:
  Branch History Table Prediction of Moving Target Branches due to Subroutine Returns. 34-42
  
• Alexander C. Klaiber, Henry M. Levy:
  An Architecture for Software-Controlled Data Prefetching. 43-53
  
• John W. C. Fu, Janak H. Patel:
  Data Prefetching in Multiprocessor Vector Cache Memories. 54-63
  
• David T. Harper III:
  Reducing Memory Contention in Shared Memory Multiprocessors. 66-73
  
• B. Ramakrishna Rau:
  Pseudo-Randomly Interleaved Memory. 74-83
  
• Kai Li, Karin Petersen:
  Evaluation of Memory System Extensions. 84-93
  
• Patrick W. Dowd:
  High Performance Interprocessor Communication through Optical Wavelength Division Multiple Access Channels. 96-105
  
• Anders Landin, Erik Hagersten, Seif Haridi:
  Race-Free Interconnection Networks and Multiprocessor Consistency. 106-115
  
• Xiaola Lin, Lionel M. Ni:
  Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks. 116-125
  
• Matthew K. Farrens, Arvin Park:
  Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. 128-137
  
• Kunle Olukotun, Trevor N. Mudge, Richard B. Brown:
  Implementing a Cache for a High-Performance GaAs Microprocessor. 138-147
  
• Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai:
  Classification and Performance Evaluation of Instruction Buffering Techniques. 150-159
  
• Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota:
  OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. 160-168
  
• Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
  An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. 170-179
  
• Chriss Stephens, Bryce Cogswell, John Heinlein, Gregory Palmer, John Paul Shen:
  Instruction Level Profiling and Evaluation of the IBM/6000. 180-189
  
• Robert T. Dimpsey, Ravishankar K. Iyer:
  Performance Prediction and Tuning on a Multiprocessor. 190-199
  
• C. W. Oehlrich, Andreas Quick:
  Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event Traces. 202-211
  
• Smaragda Konstantinidou, Lawrence Snyder:
  Chaos Router: Architecture and Performance. 212-221
  
• Shridhar B. Shukla, Dharma P. Agrawal:
  Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time Applications. 222-231
  
• Sarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer:
  Detecting Data Races on Weak Memory Systems. 234-243
  
• Eric J. Koldinger, Susan J. Eggers, Henry M. Levy:
  On the Validity of Trace-Driven Simulation for Multiprocessors. 244-253
  
• Anoop Gupta, John L. Hennessy, Kourosh Gharachorloo, Todd C. Mowry, Wolf-Dietrich Weber:
  Comparative Evaluation of Latency Reducing and Tolerating Techniques. 254-263
  
• Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu:
  IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. 266-275
  
• Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow:
  Single Instruction Stream Parallelism is Greater Than Two. 276-286
  
• Stephen W. Melvin, Yale N. Patt:
  Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. 287-296
  
• Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon:
  Comparison of Hardware and Software Cache Coherence Schemes. 298-308
  
• Richard Simoni, Mark Horowitz:
  Modeling the Performance of Limited Pointers Directories for Cache Coherence. 309-319
  
• Donna J. Quammen, D. Richard Miller:
  Flexible Register Management for Sequential Programs. 320-329
  
• David G. Bradlee, Susan J. Eggers, Robert R. Henry:
  The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy. 330-339
  
• Gregory M. Papadopoulos, Kenneth R. Traub:
  Multithreading: A Revisionist View of Dataflow Architectures. 342-351
  
• Tzi-cker Chiueh:
  Multi-Threaded Vectorization. 352-361
  
• Matthew K. Farrens, Andrew R. Pleszkun:
  Strategies for Achieving Improved Processor Throughput. 362-369
  
• Toyohiko Kagimasa, Kikuo Takahashi, Toshiaki Mori, Seiichi Yoshizumi:
  Adaptive Storage Management for Very Large Virtual/Real Storage Systems. 372-379
  
• Judith S. Hall, Paul T. Robinson:
  Virtualizing the VAX Architecture. 380-389
  
• Janaki Akella, Daniel P. Siewiorek:
  Modeling and Measurement of the Impact of Input/Output on System Performance. 390-399
  

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