21. ISCA 1994: Chicago, IL, USA

• Brad Calder, Dirk Grunwald:
  Fast and Accurate Instruction Fetch and Branch Prediction. 2-11
  
• Adam R. Talcott, Wayne Yamamoto, Mauricio J. Serrano, Roger C. Wood, Mario Nemirovsky:
  The Impact of Unresolved Branches on Branch Prediction Scheme Performance. 12-21
  
• Subbarao Palacharla, Richard E. Kessler:
  Evaluating Stream Buffers as a Secondary Cache Replacement. 24-33
  
• Norman P. Jouppi, Steven J. E. Wilton:
  Tradeoffs in Two-Level On-Chip Caching. 34-45
  
• Ashok Singhal, Aaron J. Goldberg:
  Architectural Support for Performance Tuning: A Case Study on the SPARCcenter2000. 48-59
  
• Zarka Cvetanovic, Dileep Bhandarkar:
  Characterization of Alpha AXP Performance Using TP and SPEC Workloads. 60-70
  
• Chitra Natarajan, Sanjay Sharma, Ravishankar K. Iyer:
  Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory Multiprocessor. 71-80
  
• Truman Joe, John L. Hennessy:
  Evaluating the Memory Overhead Required for COMA Architectures. 82-93
  
• Alexander C. Klaiber, Henry M. Levy:
  A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs. 94-105
  
• Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, Honghui Lu, Ramakrishnan Rajamony, Willy Zwaenepoel:
  Software Versus Hardware Shared-Memory Implementation: A Case Study. 106-117
  
• Dionisios N. Pnevmatikatos, Gurindar S. Sohi:
  Guarded Executing and Branch Prediction in Dynamic ILP Processors. 120-129
  
• Ching-Long Su, Alvin M. Despain:
  Branch with Masked Squashing in Superpipelined Processors. 130-140
  
• Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg:
  Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. 142-153
  
• Peter Steenkiste, Michael Hemy, Todd W. Mummert, Brian Zill:
  Architecture and Evaluation of High-Speed Networking Subsystem for Distributed-Memory Systems. 154-163
  
• Basem A. Nayfeh, Kunle Olukotun:
  Exploring the Design Space for a Shared-Cache Multiprocessor. 166-175
  
• Radhika Thekkath, Susan J. Eggers:
  Impact of Sharing-Based Thread Placement on Multithreaded Architectures. 176-186
  
• Fredrik Dahlgren, Michel Dubois, Per Stenström:
  Combined Performance Gains of Simple Cache Protocol Extensions. 187-197
  
• Andrew S. Huang, Gert Slavenburg, John Paul Shen:
  Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. 200-210
  
• Keith I. Farkas, Norman P. Jouppi:
  Complexity/Performance Tradeoffs with Non-Blocking Loads. 211-222
  
• Tien-Fu Chen, Jean-Loup Baer:
  A Performance Study of Software and Hardware Data Prefetching Schemes. 223-232
  
• Ann L. Drapeau, Ken Shirriff, John H. Hartman, Ethan L. Miller, Srinivasan Seshan, Randy H. Katz, Ken Lutz, David A. Patterson, Edward K. Lee, Peter M. Chen, Garth A. Gibson:
  RAID-II: A High-Bandwidth Network File Server. 234-244
  
• Mario Blaum, Jim Brady, Jehoshua Bruck, Jai Menon:
  EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID Architectures. 245-254
  
• Spencer W. Ng:
  Crosshatch Disk Array for Improved Reliability and Performance. 255-264
  
• Frederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.:
  METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. 266-277
  
• James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili:
  Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. 278-288
  
• Jae H. Kim, Ziqiang Liu, Andrew A. Chien:
  Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing. 289-300
  
• Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy:
  The Stanford FLASH Multiprocessor. 302-313
  
• David Chaiken, Anant Agarwal:
  Software-Extended Coherent Shared Memory: Performance and Cost. 314-324
  
• Steven K. Reinhardt, James R. Larus, David A. Wood:
  Tempest and Typhoon: User-Level Shared Memory. 325-336
  
• Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun:
  A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. 338-347
  
• Chung-Ho Chen, Arun K. Somani:
  A Unified Architectural Tradeoff Methodology. 348-357
  
• David Nagle, Richard Uhlig, Trevor N. Mudge, Stuart Sechrest:
  Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems. 358-369
  
• Russell W. Quong:
  Expected I-Cache Miss Rates via the Gap Model. 372-383
  
• André Seznec:
  Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. 384-393
  

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