23. ISCA 1996: Philadelphia, PA, USA

Branch Prediction

• Marius Evers, Po-Yung Chang, Yale N. Patt:
  Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. 3-11
  
• Nicholas C. Gloy:
  Cliff Young, J. Bradley Chen, Michael D. Smith: An Analysis of Dynamic Branch Prediction Schemes on System Workloads. 12-21
  
• Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge:
  Correlation and Aliasing in Dynamic Branch Predictors. 22-32
  

Shared Memory

• Steven K. Reinhardt, Robert W. Pfile, David A. Wood:
  Decoupled Hardware Support for Distributed Shared Memory. 34-43
  
• Donald Yeung, John Kubiatowicz, Anant Agarwal:
  MGS: A Multigrain Shared Memory System. 44-55
  
• Christine Morin, Alain Gefflaut, Michel Banâtre, Anne-Marie Kermarrec:
  COMA: An Opportunity for Building Fault-Tolerant Scalable Shared Memory Multiprocessors. 56-65
  

Processor/Memory Tradeoffs

• Basem A. Nayfeh, Lance Hammond, Kunle Olukotun:
  Evaluation of Design Alternatives for a Multiprocessor Microprocessor. 67-77
  
• Doug Burger, James R. Goodman, Alain Kägi:
  Memory Bandwidth Limitations of Future Microprocessors. 78-89
  
• Ashley Saulsbury, Fong Pong, Andreas Nowatzyk:
  Missing the Memory Wall: The Case for Processor/Memory Integration. 90-101
  

Cache Organization

• André Seznec:
  Don't Use the Page Number, But a Pointer To It. 104-113
  
• Toni Juan, Tomás Lang, Juan J. Navarro:
  The Difference-bit Cache. 114-120
  

Application Implications for MP Systems

• Liviu Iftode, Jaswinder Pal Singh, Kai Li:
  Understanding Application Performance on Shared Virtual Memory Systems. 122-133
  
• Chris Holt, Jaswinder Pal Singh, John L. Hennessy:
  Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory Machines. 134-145
  

Superscalar Memory Systems

• Kenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum:
  Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors. 147-157
  
• Todd M. Austin, Gurindar S. Sohi:
  High-Bandwidth Address Translation for Multiple-Issue Processors. 158-167
  

I/O and Interrupts

• Yiming Hu, Qing Yang:
  DCD - Disk Caching Disk: A New Approach for Boosting I/O Performance. 169-178
  
• Olivier Maquelin, Guang R. Gao, Herbert H. J. Hum, Kevin B. Theobald, Xinmin Tian:
  Polling Watchdog: Combining Polling and Interrupts for Efficient Message Handling. 179-188
  

Processor Microarchitecture

• Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm:
  Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. 191-202
  
• Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu:
  Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. 203-212
  
• Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya:
  Performance Comparison of ILP Machines with Cycle Time Evaluation. 213-224
  

Networks

• Jae H. Kim, Andrew A. Chien:
  Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-Cost, High-Performance Networks. 226-236
  
• Jennifer Rexford, John Hall, Kang G. Shin:
  A Router Architecture for Real-Time Point-to-Point Networks. 237-246
  
• Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, David A. Wood:
  Coherent Network Interfaces for Fine-Grain Communication. 247-258
  

Performance Evaluation and Optimization

• Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith:
  Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. 260-270
  
• Chun Xia, Josep Torrellas:
  Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. 271-282
  
• Lynn Choi, Pen-Chung Yew:
  Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study. 283-294
  

Systems

• Edward W. Felten, Richard Alpert, Angelos Bilas, Matthias A. Blumrich, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Liviu Iftode, Kai Li:
  Early Experience with Message-Passing on the SHRIMP Multicomputer. 296-307
  
• Tom Lovett, Russell M. Clapp:
  STiNG: A CC-NUMA Computer System for the Commercial Marketplace. 308-317
  

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