25. ISCA 1998: Barcelona, Spain
Mateo Valero, Gurindar S. Sohi, Doug DeGroot (Eds.): Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998. IEEE Computer Society 1998 ISBN 0-8186-8491-7
Machine Measurement
- Luiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion: Memory System Characterization of Commercial Workloads. 3-14
- Kimberly Keeton, David A. Patterson, Yong Qiang He, Roger C. Raphael, Walter E. Baker: Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads. 15-26
- Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad: Execution Characteristics of Desktop Applications on Windows NT. 27-38
- Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh: An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. 39-50
Program Behavior
- Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. 52-61
- Eitan Federovsky, Meir Feder, Shlomo Weiss: Branch Prediction Based on Universal Data Compression Algorithms. 62-72
Graphics and IO
- Michael Cox, Narendra Bhandri, Michael Shantz: Multi-Level Texture Caching for 3D Graphics Hardware. 86-97
- Hans Eberle, Erwin Oertli: Switcherland: A QoS Communication Architecture for Workstation Clusters. 98-108
- Guillermo A. Alvarez, Walter A. Burkhard, Larry J. Stockmeyer, Flaviu Cristian: Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism. 109-120
Speculation
- Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun: Confidence Estimation for Speculation Control. 122-131
- Srilatha Manne, Artur Klauser, Dirk Grunwald: Pipeline Gating: Speculation Control for Energy Reduction. 132-141
Prediction Techniques
- Toni Juan, Sanji Sanjeevan, Juan J. Navarro: Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction. 155-166
Memory Management
- Mark Oskin, Frederic T. Chong, Timothy Sherwood: Active Pages: A Computation Model for Intelligent Memory. 192-203
- Mark R. Swanson, Leigh Stoller, John B. Carter: Increasing TLB Reach Using Superpages Backed by Shadow Memory. 204-213
Predication and Multipath Execution
- David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu: Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture. 227-237
- Artur Klauser, Abhijit Paithankar, Dirk Grunwald: Selective Eager Execution on the PolyPath Architecture. 250-259
Processor Microarchitecture
- Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. 262-271
- Freddy Gabbay, Avi Mendelson: The Effect of Instruction Fetch Bandwidth on Value Prediction. 272-281
- David H. Albonesi: Dynamic IPC/Clock Rate Optimization. 282-292
- Yinong Zhang, George B. Adams III: Performance Modeling and Code Partitioning for the DS Architecture. 293-304
Parallel Machines
- Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee: Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. 306-317
- Gheith A. Abandah, Edward S. Davidson: Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. 318-329
- Matthias A. Blumrich, Richard Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li, Margaret Martonosi, Robert A. Shillner: Design Choices in the SHRIMP System: An Empirical Study. 330-341
- Vijayaraghavan Soundararajan, Mark Heinrich, Ben Verghese, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy: Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors. 342-355
Caches and Memory Systems
- Sanjeev Kumar, Christopher B. Wilkerson: Exploiting Spatial Locality in Data Caches Using Spatial Footprints. 357-368
- William L. Lynch, Gary Lauterbach, Joseph I. Chamdani: Low Load Latency Through Sum-Addressed Memory (SAM). 369-379
- Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood: Analytic Evaluation of Shared-memory Systems with ILP Processors. 380-391
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