ISCAS 2005: Kobe, Japan - Volume 1

• Aditya Bansal, Kaushik Roy:
  Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. 1-4
  
• Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
  Limits to performance spread tuning using adaptive voltage and body biasing. 5-8
  
• James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De:
  Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. 9-12
  
• Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba:
  Device technology for body biasing scheme. 13-16
  
• Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara:
  Optimum threshold-voltage tuning for low-power, high-performance microprocessor. 17-20
  
• Ruchir Puri, David S. Kung, Leon Stok:
  Minimizing power with flexible voltage islands. 21-24
  
• Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga:
  Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. 25-28
  
• Mahmoud Elassal, Ashok Kumar, Magdy Bayoumi:
  A systematic framework for high throughput MAP decoder VLSI architectures. 29-32
  
• Saman S. Abeysekera, Charoensak Charayaphan:
  System on chip FPGA design of an FM demodulator using a Kalman band-pass sigma-delta architecture. 33-36
  
• Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser:
  High level hardware/software communication estimation in shared memory architecture. 37-40
  
• Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan:
  A novel low-power reconfigurable FFT processor. 41-44
  
• Bradley R. Quinton, Steven J. E. Wilton:
  Concentrator access networks for programmable logic cores on SoCs. 45-48
  
• Maria-Gabriella Di Benedetto, Guerino Giancola:
  A collision-based model for multi user interference in impulse radio UWB networks. 49-52
  
• Luca Reggiani, Gian Mario Maggio:
  On the acquisition time for serial and parallel code search in UWB impulse radio. 53-56
  
• Chun Yi Lee, Christofer Toumazou:
  Ultra-low power UWB for real time biomedical wireless sensing. 57-60
  
• Won Namgoong, Lei Feng:
  Digitizing of UWB signals based on frequency channelization. 61-64
  
• Sang-Min Kim, Jun Tang, Keshab K. Parhi:
  Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems. 65-68
  
• Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy:
  A novel covalent redundant binary Booth encoder. 69-72
  
• Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino:
  A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. 73-76
  
• Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang:
  A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. 77-80
  
• Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo:
  A framework for the design of error-aware power-efficient fixed-width Booth multipliers. 81-84
  
• Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar:
  A novel multiplexer based truncated array multiplier. 85-88
  
• James E. Stine, Michael J. Schulte:
  A combined two's complement and floating-point comparator. 89-92
  
• Yici Cai, Yibo Wang, Xianlong Hong:
  A global interconnect optimization algorithm under accurate delay model using solution space smoothing. 93-96
  
• Yiqian Zhang, Xianlong Hong, Yici Cai:
  An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. 97-100
  
• Xinjie Wei, Yici Cai, Xianlong Hong:
  Zero skew clock routing with tree topology construction using simulated annealing method. 101-104
  
• Hao Yu, Lei He:
  A sparsified vector potential equivalent circuit model for massively coupled interconnects. 105-108
  
• Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn:
  An efficient algorithm for simultaneous wire permutation, inversion, and spacing. 109-112
  
• Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
  Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. 113-116
  
• Alberto Saiz-Vela, Pedro Lluís Miribel-Català, Manel Puig-Vidal, Josep Samitier:
  An electron mobility independent pulse skipping regulator for a programmable CMOS charge pump. 117-120
  
• Chiara Boffino, Alessandro Cabrini, Osama Khouri, Guido Torelli:
  High-efficiency control structure for CMOS flash memory charge pumps. 121-124
  
• Mark Hooper, Matt Kucic, Paul E. Hasler:
  Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuits. 125-128
  
• Heng-Ming Hsu, Tai-Hsing Lee:
  Optimum quiescent point of integrated power CMOS transistor for wireless portable applications. 129-132
  
• Mohammad R. Hoque, T. Ahmad, Todd McNutt, H. Alan Mantooth, Mohammad M. Mojarradi:
  Design technique of an on-chip, high-voltage charge pump in SOI. 133-136
  
• Eugenio Culurciello, Philippe O. Pouliquen, Andreas G. Andreou, Kim Strohbehn, Steven E. Jaskulek:
  A monolithic isolation amplifier in silicon-on-insulator CMOS. 137-140
  
• Raimon Casanova, Junajo Lacort, Ángel Dieguez, Anna Arbat, Manel Puig, Josep Samitier, Marc Nierlich, Oliver Steinmetz, Oliver Scholz:
  A specific integrated controller for nanomicroscopy and cellular manipulation. 141-144
  
• Chris Clarke, John Taylor, Robert Rieger, Nick Donaldson:
  A distributed neural signal sensor system. 145-148
  
• Jierong Cheng, Say Wei Foo, Shankar M. Krishnan:
  Automatic detection of region of interest and center point of left ventricle using watershed segmentation. 149-151
  
• Chin-Teng Lin, Yu-Chieh Chen, Ruei-Cheng Wu, Sheng-Fu Liang, Teng-Yi Huang:
  Assessment of driver's driving performance and alertness using EEG-based fuzzy neural networks. 152-155
  
• Sheng-Fu Liang, Chin-Teng Lin, Ruei-Cheng Wu, Teng-Yi Huang, Wen-Hung Chao:
  Classification of driver's cognitive responses from EEG analysis. 156-159
  
• Takehiro Ito, Xiao Zhou, Takao Nishizeki:
  Partitioning graphs of supply and demand. 160-163
  
• Krishnaiyan Thulasiraman, Ying Xiao, Guoliang Xue:
  Advances in QoS path(s) selection problem. 164-167
  
• Tomiyuki Fukunaga, Qi-Wei Ge, Mitsuru Nakata:
  On generating elementary T-invariants of Petri nets by linear programming. 168-171
  
• Daisuke Takafuji, Toshimasa Watanabe:
  Hierarchical extraction of a spanning planar subgraph maintaining clockwise directedness of cycles. 172-175
  
• Hiroshi Tamura, Futoshi Tasaki, Masakazu Sengoku, Shoji Shinoda:
  Scheduling problems for a class of parallel distributed systems. 176-179
  
• Satoshi Tayu, Patrik Hurtig, Yoshiyasu Horikawa, Shuichi Ueno:
  On the three-dimensional channel routing. 180-183
  
• Brian P. Ginsburg, Anantha P. Chandrakasan:
  An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. 184-187
  
• Harri Lampinen, Pauli Perälä, Olli Vainio:
  Novel successive-approximation algorithms. 188-191
  
• Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata:
  A 1V supply successive approximation ADC with rail-to-rail input voltage range. 192-195
  
• David Marche, Yves Gagnon, Yvon Savaria:
  . A new switch compensation technique for inverted R-2R ladder DACs. 196-199
  
• Hamid Movahedian, Mehrdad Sharif Bakhtiar:
  A new offset cancellation technique for folding ADC. 200-203
  
• Tomás Lahoz, Enrique Barajas, José Luis González:
  Characterization and noise analysis of a 12-bit current steering digital-to-analog converter. 204-207
  
• Belén Calvo, Maria Teresa Sanz, Santiago Celma:
  High linear digitally programmable gain amplifier. 208-211
  
• Chih-Yun Liu, Yi-Jan Emery Chen, Deuk Hyoun Heo:
  Impact of bias schemes on Doherty power amplifiers. 212-215
  
• Mikko Loikkanen, Juha Kostamovaara:
  High current CMOS operational amplifier. 216-219
  
• Yasutaka Haga, Hashem Zare-Hoseini, Laurence Berkovi, Izzet Kale:
  Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique. 220-223
  
• Tong Ge, Meng Tong Tan, Joseph Sylvester Chang:
  Design and analysis of a micropower low-voltage bang-bang control class D amplifier. 224-227
  
• Christian Falconi, Giuliano Guarino, Arnaldo D'Amico:
  Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [voltage regulator example]. 228-231
  
• Jeffrey Harrison:
  Formal synthesis of circuits using linear matrix inequalities. 232-235
  
• Antônio Carlos M. de Queiroz:
  Multiple resonance networks with incomplete energy transfer and operating with zero-state response. 236-239
  
• Kai-Sheng Lu, Xiao-Yu Feng, Guo-Zhang Gao:
  The separability, reducibility and controllability of RLCM networks over F(z). 240-243
  
• David G. Haigh, Paul M. Radmore:
  Symbolic passive-RC circuit synthesis by admittance matrix expansion. 244-247
  
• David G. Haigh:
  Symbolic active-RC circuit synthesis by admittance matrix expansion. 248-251
  
• Rogelio Palomera-Garcia:
  Generation of equivalent circuits by FTFN relocation. 252-255
  
• Mitsuji Muneyasu, Osamu Hisayasu, Kensaku Fujii, Takao Hinamoto:
  An active noise control system based on simultaneous equations method without auxiliary filters. 256-259
  
• Yegui Xiao, Liying Ma, Khashayar Khorasani, Akira Ikuta, Li Xu:
  A filtered-X RLS based narrowband active noise control system in the presence of frequency mismatch. 260-263
  
• Muhammad Tahir Akhtar, Masahide Abe, Masayuki Kawamata:
  A method for online secondary path modeling in active noise control systems. 264-267
  
• Say Wei Foo, T. N. Senthilkumar, C. Averty:
  Active noise cancellation headset. 268-271
  
• Naoto Sasaoka, Keisuke Sumi, Yoshio Itoh, Kensaku Fujii:
  A new noise reduction system based on ALE and noise reconstruction filter. 272-275
  
• Woon S. Gan, Sen M. Kuo, Jin Wei Feng:
  Adaptive noise equalizer with equal-loudness compensation. 276-279
  
• Xiang Li, Hildegard Meyer-Ortmanns, Xiaofan Wang:
  Chaotic and periodic spreading dynamics in discrete small-world networks. 280-283
  
• Zhengping Fan, Guanrong Chen:
  Pinning control of scale-free complex networks. 284-287
  
• Chunguang Li, Jin-Qing Fang:
  On-off intermittency in small-world networks of chaotic maps. 288-291
  
• Chai Wah Wu:
  Agreement and consensus problems in groups of autonomous agents with linear dynamics. 292-295
  
• Maide Bucolo, Francesca Conti, Luigi Fortuna, Mattia Frasca:
  3D dynamical networks to emulate complex neural phenomena. 296-299
  
• Jinhu Lu, Henry Leung:
  Synchronization: a fundamental phenomenon in complex dynamical networks. 300-303
  
• Debing Liu, Yuwen He, Shipeng Li, Qingming Huang, Wen Gao:
  Linear transform based motion compensated prediction for luminance intensity changes. 304-307
  
• Changsung Kim, C. C. Jay Kuo:
  A feature-based approach to fast H.264 intra/inter mode decision. 308-311
  
• Hongtao Yu, Zhiping Lin, Feng Pan:
  An improved rate control algorithm for H.264. 312-315
  
• Cixun Zhang, Jian Lou, Lu Yu, Jie Dong, Wai-kuen Cham:
  The technique of pre-scaled integer transform. 316-319
  
• Panos Nasiopoulos, Lino Coria-Mendoza, Hassan Mansour, Adarsh Golikeri:
  An improved error concealment algorithm for intra-frames in H.264/AVC. 320-323
  
• Thomas Wedi, Stefan Wittmann:
  Quantization offsets for video coding. 324-327
  
• Meng-Guang Tsai, Kuen-Suey Hou, Hen-Wai Tsao:
  Iterative tri-stage decoding for turbo codes in partial response channels. 328-331
  
• Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel:
  . Analog slice turbo decoding. 332-335
  
• Stephen Bates, Gary Block:
  A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders. 336-339
  
• Qingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao:
  Low complexity parallel Chien search architecture for RS decoder. 340-343
  
• Matthias Kamuf, John B. Anderson, Viktor Öwall:
  Area and power efficient trellis computational blocks in 0.13µm CMOS. 344-347
  
• Rajendra S. Katti, Xiaoyu Ruan:
  S-code: new distance-3 MDS array codes. 348-351
  
• A. Prasad Vinod, Edmund Ming-Kit Lai:
  Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receivers. 352-355
  
• Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng:
  Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. 356-359
  
• Yumi Takizawa, Cindy Bernadeth Tjitrosoewarno, Atsushi Fukasawa:
  Multi-user receiver using conjugate gradient method for wideband CDMA. 360-363
  
• Lucian-Vasile Stoica, Sakari Tiuraniemi, Heikki Repo, Ian Oppermann:
  An ultra wideband low complexity circuit transceiver architecture for sensor networks. 364-367
  
• Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao:
  A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. 368-371
  
• Ehab Shoukry, Madeleine Mony, David V. Plant:
  Design of a fully integrated array of high-voltage digital-to-analog converters. 372-375
  
• Lin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do:
  A novel methodology for the design of LC tank VCO with low phase noise. 376-379
  
• Yuan Yao, Yin Shi, Foster F. Dai:
  A novel low-power input-independent MOS AC/DC charge pump. 380-383
  
• Zhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu:
  Large tuning band range of high frequency filter for wireless applications. 384-387
  
• Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D'Amico, Andrea Baschirotto:
  Behavioral analysis and dimensioning of UMTS transmitters baseband blocks. 388-391
  
• Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins:
  A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. 392-395
  
• Jiangnan Yan, Yuanjin Zheng, Yong Ping Xu:
  A novel DC-offset cancelling circuit for DCR. 396-399
  
• Chiara Ghidini, J. G. Aranda, Danilo Gerna, K. Kelliher, Christoph Baumhof:
  A digitally programmable on-chip RC-oscillator in 0.25µm CMOS logic process. 400-403
  
• Si-Weng Fok, Phillip Ngai Cheong, Kam-Weng Tam, Rui Paulo Martins:
  A novel microstrip bandpass filter design using asymmetric parallel coupled-line. 404-407
  
• Yongru Gu, Keshab K. Parhi:
  Pipelining Tomlinson-Harashima precoders. 408-411
  
• Sebastián López, Félix Tobajas, A. Villar, V. de Armas, José Francisco López, Roberto Sarmiento:
  Low cost efficient architecture for H.264 motion estimation. 412-415
  
• Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner:
  Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip. 416-419
  
• Wai-Chi Fang, C. Le, S. Taft:
  On-board fault-tolerant SAR processor for spaceborne imaging radar systems. 420-423
  
• Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi:
  Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. 424-427
  
• Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin:
  Design space exploration on heterogeneous network-on-chip. 428-431
  
• Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung:
  A simple and cost effective video encoder with memory-reducing CAVLC. 432-435
  
• Xuequn Li, Haleh Vahedi, Radu Muresan, Stefano Gregori:
  An integrated current flattening module for embedded cryptosystems. 436-439
  
• Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
  A pseudo-differential CMOS receiver insensitive to input common mode level. 440-443
  
• Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen:
  Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. 444-447
  
• Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti:
  High-speed CMOS-to-ECL pad driver in 0.18µm CMOS. 448-451
  
• Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga:
  A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter. 452-455
  
• Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen:
  Case study of interconnect analysis for standing wave oscillator design. 456-459
  
• Johan Lambie, Francesc Moll Echeto, José Luis González, Antonio Rubio:
  Asynchronous pulse logic cell for threshold logic and Boolean networks. 460-463
  
• Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra:
  Cascode buffer for monolithic voltage conversion operating at high input supply voltages. 464-467
  
• David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler:
  Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. 468-471
  
• Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis:
  A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. 472-475
  
• Bogdan J. Falkowski, Cheng Fu:
  Quaternary arithmetic helix transforms based on Kronecker product. 476-479
  
• Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja:
  Generalized fastest linearly independent arithmetic transforms. 480-483
  
• Bogdan J. Falkowski, Shixing Yan:
  Fixed sign Walsh transform and its iterative hardware architecture. 484-487
  
• Bogdan J. Falkowski, Cheng Fu:
  Generation of linearly independent transforms over GF(4). 488-491
  
• Xiaolang Yan, Ying Qin, Ye Yang, Haitong Ge:
  A high performance architecture of EBCOT encoder in JPEG 2000. 492-495
  
• A. Prasad Vinod, Edmund Ming-Kit Lai:
  Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters. 496-499
  
• Tian-Bo Deng:
  Complex-coefficient variable filter design using successive vector-array-decomposition. 500-503
  
• Tian-Bo Deng:
  Non-iterative WLS design of allpass variable fractional-delay digital filters. 504-507
  
• Masayoshi Nakamoto, Yuji Maejima, Takao Hinamoto:
  Discrete optimization for error feedback network using lower bound estimation. 508-511
  
• Chia-Yu Yao, Chiang-Ju Chien:
  Design of a square-root-raised-cosine FIR filter by a recursive method. 512-515
  
• Jinxin Hao, Gang Li, Jun Wu:
  Pole deviation analysis for digital systems based on second order perturbation theory [digital filter example]. 516-519
  
• Ling Cen, Yong Lian:
  A hybrid GA for the design of multiplication-free frequency response masking filters [FIR digital filters]. 520-523
  
• Dirk S. Waldhauser, Christoph Saas, Josef A. Nossek:
  Pulse shaping with bireciprocal wave digital lattice filters. 524-527
  
• Masahide Abe, Hiroki Arai, Masayuki Kawamata:
  Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation. 528-531
  
• Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung:
  A novel 2D filter design methodology. 532-535
  
• Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster:
  Synthesis of reconfigurable multiplier blocks: part I - fundamentals. 536-539
  
• Süleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster:
  Synthesis of reconfigurable multiplier blocks: part - II algorithm. 540-543
  
• Li-Hsun Chen, Oscal T.-C. Chen:
  A hardware-efficient FIR architecture with input-data and tap folding. 544-547
  
• Grace Y. Cho, Louis G. Johnson, Michael A. Soderstrand:
  Residue number system implementations of complex heterodyne tunable filters. 548-551
  
• Ashok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi:
  Low complexity decimation filter for multi-standard digital receivers. 552-555
  
• Glen W. Mabey, Tamal Bose, Mei Chen:
  Stability of a shift-variant 2-D state-space digital filter. 556-559
  
• Chun-Chi Chen, Wen-Fu Lu, Chin-Chung Tsai, Poki Chen:
  A time-to-digital-converter-based CMOS smart temperature sensor. 560-563
  
• Takashi Yoshida, Arimitsu Yokota, Hideki Kashiyama, Takayuki Hamamoto:
  High-speed sensing system for depth estimation based on depth-from-focus by using smart imager. 564-567
  
• J. L. D. Gonzalez, Daniel C. Sadowski, Karan V. I. S. Kaler, Martin P. Mintchev, Orly Yadid-Pecht:
  A CMOS imager for light blobs detection and processing. 568-571
  
• Fabrizio De Nisi, David Stoppa, Mauro Scandiuzzo, Lorenzo Gonzo, Lucio Pancheri, Gian-Franco Dalla Betta:
  Design of electro-optical demodulating pixel in CMOS technology. 572-575
  
• Shengke Zeng, John R. Powers, Larry L. Jackson, David L. Conover:
  Digital measurement of human proximity to electrical power circuit by a novel amplitude-shift-keying radio-frequency receiver. 576-579
  
• Alexander Fish, Evgeny Avner, Orly Yadid-Pecht:
  Low-power global/rolling shutter image sensors in silicon on sapphire technology. 580-583
  
• Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale:
  Low power current mode ADC for CMOS sensor IC. 584-587
  
• Vadim Alexander Milirud, Leonid Fleshel, Wenjing Zhang, Graham A. Jullien, Orly Yadid-Pecht:
  A wide dynamic range CMOS active pixel sensor with frame difference. 588-591
  
• Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De:
  Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. 592-595
  
• Guoqing Chen, Eby G. Friedman:
  Low power repeaters driving RLC interconnects with delay and bandwidth constraints. 596-599
  
• Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
  Low-leakage repeaters for NoC interconnects. 600-603
  
• Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif:
  Power-aware global signaling strategies. 604-607
  
• Vidyasagar Nookala, Sachin S. Sapatnekar:
  Designing optimized pipelined global interconnects: algorithms and methodology impact. 608-611
  
• Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman:
  Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. 612-615
  
• Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi:
  Battery-aware dynamic voltage scaling in multiprocessor embedded system. 616-619
  
• Mikhail Popovich, Eby G. Friedman:
  Noise coupling in multi-voltage power distribution systems with decoupling capacitors. 620-623
  
• Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale:
  A 16-bit low-power microcontroller with monolithic MEMS-LC clocking. 624-627
  
• Yuichi Nakamura, Takeshi Yoshimura:
  A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. 628-631
  
• Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara:
  An LSI system with locked in temperature insensitive state achieved by using body bias technique. 632-635
  
• Ming Zhang, Naresh R. Shanbhag:
  An energy-efficient circuit technique for single event transient noise-tolerance. 636-639
  
• Chi-Fu Huang, Li-Chu Lo, Yu-Chee Tseng, Wen-Tsuen Chen:
  Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networks. 640-643
  
• Eugenio Culurciello, Thiago Teixeira, Andreas G. Andreou:
  Event-based imaging with active illumination in sensor networks. 644-647
  
• Niwat Thepvilojanapong, Yoshito Tobe, Kaoru Sezaki:
  On the construction of efficient data gathering tree in wireless sensor networks. 648-651
  
• Cesare Alippi, Alan Mottarella, Giovanni Vanini:
  A RF map-based localization algorithm for indoor environments. 652-655
  
• Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan:
  A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. 656-659
  
• Qiang Liu, Dong Tong, Xu Cheng:
  Non-interleaving architecture for hardware implementation of modular multiplication. 660-663
  
• Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang:
  A new design method to modulo 2/sup n/-1 squaring. 664-667
  
• James E. Stine, Christopher R. Babb, Vibhuti B. Dave:
  Constant addition utilizing flagged prefix structures. 668-671
  
• Kei-Yong Khoo, Alan N. Willson Jr.:
  Efficient VLSI implementation of N/N integer division. 672-675
  
• Ge Zhang, Zichu Qi, Weiwu Hu:
  A novel design of leading zero anticipation circuit with parallel error detection. 676-679
  
• Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin:
  High-level synthesis under I/O timing and memory constraints. 680-683
  
• Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan:
  A low power scheduling method using dual V/sub dd/ and dual V/sub th/. 684-687
  
• Ling Wang, Yingtao Jiang, Yu Zhang, Ru Chen:
  A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages. 688-691
  
• Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
  A heuristic approach for multiple restricted multiplication. 692-695
  
• Junjuan Xu, Jason Cong, Xu Cheng:
  Lower-bound estimation for multi-bitwidth scheduling. 696-699
  
• Koji Ohashi, Mineo Kaneko:
  Statistical schedule length analysis in asynchronous datapath synthesis. 700-703
  
• Antti Heiskanen, Timo Rahkonen:
  Comparison of two class E amplifiers for EER transmitter. 704-707
  
• Tadashi Suetsugu, Marian K. Kazimierczuk:
  Steady-state behavior of class E amplifier outside designed conditions. 708-711
  
• Tadashi Suetsugu, Marian K. Kazimierczuk:
  Voltage-clamped class E amplifier with transmission-line transformer. 712-715
  
• Siu Chung Wong, Chi K. Michael Tse:
  Optimum design of very low distortion class E power amplifiers. 716-719
  
• Hiroyuki Hase, Hiroo Sekiya, Jianming Lu, Takashi Yahagi:
  Resonant DC/DC converter with class E oscillator. 720-723
  
• Alain Salles, Bruno Estibals, David Bourrier, Corinne Alonso:
  Planar inductors with interleaved conductors for integrated power applications. 724-727
  
• Aleksandra Rankov, Esther Rodríguez-Villegas, Michael J. Lee:
  A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensors. 728-731
  
• Torsten Lehmann, Yashodhan Moghe:
  On-chip active power rectifiers for biomedical applications. 732-735
  
• Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng:
  A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. 736-739
  
• Sunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo:
  A 0.9-V 67-µW analog front-end using adaptive-SNR technique for digital hearing aid. 740-743
  
• Iasonas F. Triantis, Andreas Demosthenous:
  A BiCMOS ENG amplifier with high SIR output. 744-747
  
• Robert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter J. Langlois, Nick Donaldson:
  10-channel very low noise ENG amplifier system using CMOS technology. 748-751
  
• Toshiya Mashima, Takanori Fukuoka, Satoshi Taoka, Toshimasa Watanabe:
  Minimum augmentation to bi-connect specified vertices of a graph with upper bounds on vertex-degree. 752-755
  
• Mamoru Sakamoto, Toshiyuki Miyamoto, Sadatoshi Kumagai:
  A modeling method of a rule based control system with hierarchical Petri net. 756-759
  
• Atsushi Ohta, Kohkichi Tsuji, Tomiji Hisamura:
  Minimal time reachability problem of some subclasses of timed Petri nets. 760-763
  
• Kai-Sheng Lu, Guo-Zhang Gao:
  The node voltage equations and structural conditions of observability for RLC networks over F(z). 764-767
  
• Tetsuo Nishi, Masato Ogata:
  Graph-theoretic approach to the design of four-switch DC-DC converters. 768-771
  
• Sastry Mks:
  Simplified algorithm to determine break point realys and relay coordination based on network topology [for realys read relays]. 772-775
  
• Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D'Amico, Andrea Baschirotto:
  A low-distortion 1.2 V DAC+filter for transmitters in wireless applications. 776-779
  
• Po-Ming Lee, Hung-Yi Chen:
  Adjustable gamma correction circuit for TFT LCD. 780-783
  
• Beatriz Olleta, Hanjun Jiang, Degang Chen, Randall L. Geiger:
  A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test. 784-787
  
• Georgi I. Radulov, Patrick J. Quinn, Johannes A. Hegt, Arthur H. M. van Roermund:
  A start-up calibration method for generic current-steering D/A converters with optimal area solution. 788-791
  
• Zhongjun Yu, Degang Chen, Randall L. Geiger, Ioannis Papantonopoulos:
  Pipeline ADC linearity testing with dramatically reduced data capture time. 792-795
  
• João Goes, Nuno F. Paulino, Guiomar Evans:
  On-chip built-in self-test of video-rate ADCs using Gaussian noise. 796-799
  
• Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez:
  A 0.18µm CMOS low-noise elliptic low-pass continuous-time filter. 800-803
  
• Shu-Hui Tu, J. Neil Ross:
  Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum components. 804-807
  
• Drazen Jurisic, Neven Mijat, George S. Moschytz:
  Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networks. 808-811
  
• Tomoyuki Tanaka, Sungwoo Cha, Shinsaku Shimizu, Tsukasa Ida, Hiroaki Ishihara, Toshimasa Matsuoka, Kenji Taniguchi, Akashi Sugimori, Hiroki Hihara:
  A widely tunable Gm-C filter using tail current offset in two differential pairs. 812-815
  
• Satoshi Hirano, Aya Sato, Tadashi Kitamura:
  A comparison approach of lowpass type wave active filter using unified circuit block. 816-819
  
• Gaurav Chandra, Preetam Tadeparthy, Prakash Easwaran:
  Single amplifier bi-quadratic filter topologies in transimpedance configuration. 820-823
  
• Chien-Cheng Tseng, Tsung-Ming Hwang:
  Quantum circuit design of discrete Hartley transform using recursive decomposition formula. 824-827
  
• Chien-Cheng Tseng, Tsung-Ming Hwang:
  Quantum circuit design of 8×8 discrete cosine transform using its fast computation flow graph. 828-831
  
• Magdy T. Hanna, Nabila P. Attalla Seif, M. Waleed Abd El Maguid Ahmed:
  Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrix. 832-835
  
• Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy:
  An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structure. 836-839
  
• Alfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek:
  Design of wavelet filters based on digital complex allpass filters. 840-843
  
• Liang Tao, Hon Keung Kwan:
  Block time-recursive discrete Gabor transform implemented by unified parallel lattice structures. 844-847
  

Last update Thu May 23 17:27:22 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page