ISCAS 2005: Kobe, Japan - Volume 2

• Andreas Spanias, Venkatraman Atti:
  Rate determination based on perceptual loudness. 848-851
  
• Benny Sallberg, Mattias Dahl, Henrik Akesson, Ingvar Claesson:
  A mixed analog-digital hybrid for speech enhancement purposes. 852-855
  
• Hai Quang Dam, Sven Nordholm, Hai Huyen Dam, Siow Yong Low:
  Adaptive beamformer for hands-free communication system in noisy environments. 856-859
  
• Sourabh Ravindran, David V. Anderson:
  Audio classification and scene recognition and for hearing aids. 860-863
  
• Yu Shao, Chip-Hong Chang:
  A versatile speech enhancement system based on perceptual wavelet denoising. 864-867
  
• Abhijeet Sangwan, Wei-Ping Zhu, M. Omair Ahmad:
  Improved voice activity detection via contextual information and noise suppression. 868-871
  
• Hiroshi Fujisaki, Gerhard Keller:
  Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chains. 872-875
  
• Ji Yao, Anthony J. Lawrance:
  Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systems. 876-879
  
• Chengqing Li, Xinxiao Li, Shujun Li, Guanrong Chen:
  Cryptanalysis of a multistage encryption system. 880-883
  
• Yutaka Jitsumatsu, Tohru Kohda:
  Design of code-matched receiver for DS/CDMA communications. 884-887
  
• Slobodan Kozic, Thomas Schimming:
  Coded modulation based on higher dimensional chaotic maps. 888-891
  
• Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
  Long period pseudo random bit generators derived from a discretized chaotic map. 892-895
  
• Haiyan Shu, Lap-Pui Chau:
  Frame size selection in video downsizing transcoding application. 896-899
  
• Deepak P. Nayak, Dipan B. Mehta, Uday B. Desai:
  A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcoders. 900-903
  
• Viet Anh Nguyen, Yap-Peng Tan:
  Efficient video transcoding between H.263 and H.264/AVC standards. 904-907
  
• Kai-Tat Fung, Wan-Chi Siu:
  Low complexity H.263 to H.264 video transcoding using motion vector decomposition. 908-911
  
• Mei Kodama, Shunya Suzuki:
  Consideration of transcoding using updatable scalability for selective quality video content delivery method. 912-915
  
• Carlos Salazar-Lazaro, Trac D. Tran:
  Flexible resizing algorithms for video transcoding. 916-919
  
• Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue:
  A low-power, 20-Gb/s continuous-time adaptive passive equalizer. 920-923
  
• Norbert Neurohr, Matthias Schoebinger, Edoardo Prete, Anthony Sanders:
  Adaptive decision-feedback equalization for band-limited high-speed serial links. 924-927
  
• Junhua Tian, Bo Shen, Zheng Li, Jianing Su, Qianling Zhang:
  Joint carrier recovery and adaptive equalization for high-order QAM. 928-931
  
• Miguel A. Melgarejo, Fredy Olarte, Pedro Ladino:
  Hardware realization of fuzzy adaptive filters for non linear channel equalization. 932-935
  
• Anthony Chan Carusone:
  Jitter equalization for binary baseband communication. 936-939
  
• Ting-An Lin, Chen-Yi Lee:
  Predictive equalizer design for DVB-T system. 940-943
  
• Jeong-Hyu Yang, Chang-Su Kim, Sang-Uk Lee:
  Progressive coding of 3D dynamic mesh sequences using spatiotemporal decomposition. 944-947
  
• Jingliang Peng, Sheng Yang, C. C. Jay Kuo:
  Progressive lossless 3D mesh encoder with octree-based space partitioning. 948-951
  
• Hao-Song Kong, Anthony Vetro, Toshihiko Hata, Naoki Kuwahara:
  Fast region-of-interest transcoding for JPEG 2000 images. 952-955
  
• Jae-Young Sim, Sang-Uk Lee, Chang-Su Kim:
  Construction of regular 3D point clouds using octree partitioning and resampling. 956-959
  
• Dong Wang, Cedric Nishan Canagarajah, David R. Bull:
  Slice group based multiple description video coding with three motion compensation loops. 960-963
  
• Peng Wang, Rui Cai, Shi-Qiang Yang:
  Improving classification of video shots using information-theoretic co-clustering. 964-967
  
• Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
  The upper bound of the second-order modes of linear state-space systems [digital filter example]. 968-971
  
• Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
  A novel property of the second-order modes of discrete-time systems under variable transformation. 972-975
  
• Aziz S. Inan, Peter M. Osterberg:
  Special singularity integrals encountered in electric circuits [RLC circuit examples]. 976-979
  
• Alexei S. Adalev, Nikolai V. Korovkin, Masashi Hayakawa:
  Identification of electric circuits: problems and methods of solution accuracy enhancement. 980-983
  
• Luis Nero Alves, Rui L. Aguiar:
  On the effect of time delays in negative feedback amplifiers. 984-987
  
• Svante Signell:
  Jittered uniform sampling - examples. 988-991
  
• Barbara Cannas, Alessandra Fanni, Augusto Montisci:
  Testability evaluation for analog linear circuits via transfer function analysis. 992-995
  
• Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch:
  Synthesis of MITE log-domain filters with unique operating points. 996-999
  
• Soliman A. Mahmoud:
  Low voltage high current gain CMOS digitally controlled fully differential CCII [variable gain amplifier application example]. 1000-1003
  
• Boonchai Boonchu, Wanlop Surakampontorn:
  A new NMOS four-quadrant analog multiplier. 1004-1007
  
• Juan M. Carrillo, J. Francisco Duque-Carrillo, Antonio B. Torralba, Ramón González Carvajal:
  Class-AB rail-to-rail CMOS analog buffer. 1008-1011
  
• Eduardo Rapoport, Fernando Antonio Pinto Baruqui, Antonio Petraglia:
  IC design of an analog tunable crossover network. 1012-1015
  
• Varakorn Kasemsuwan, Teerawat Arthansiri, Hyung Keun Ahn:
  A ± 1.5 V high frequency four quadrant current multiplier. 1016-1019
  
• Fábio A. Pereira, Mário C. G. de Oliveira, Ana Isabela Araújo Cunha:
  CMOS analog current-mode multiplier based on the advanced compact MOSFET model. 1020-1023
  
• T. Yasuda:
  On-chip temperature sensor with high tolerance for process and temperature variation. 1024-1027
  
• Yaxiong Zhang, Alister Hamilton:
  A current mode Palmo cell for programmable analogue signal processing. 1028-1031
  
• Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu:
  A memory-reduced log-MAP kernel for turbo decoder. 1032-1035
  
• Hanho Lee:
  An ultra high-speed Reed-Solomon decoder. 1036-1039
  
• Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang:
  A new low-power turbo decoder using HDA-DHDD stopping iteration. 1040-1043
  
• Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli:
  Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. 1044-1047
  
• Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay:
  Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric. 1048-1050
  
• Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed:
  A new reconfigurable modem architecture for 3G multi-standard wireless communication systems. 1051-1054
  
• Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang:
  A 12.5 Gbps CMOS input sampler for serial link receiver front end. 1055-1058
  
• Zeynep Toprak Deniz, Yusuf Leblebici:
  Low-power current mode logic for improved DPA-resistance in embedded systems. 1059-1062
  
• Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim:
  A new level-up shifter for high speed and wide range interface in ultra deep sub-micron. 1063-1065
  
• Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti:
  A novel CMOS logic style with data independent power consumption. 1066-1069
  
• Kuo-Hsing Cheng, Chen-Lung Wu, Yu-lung Lo, Chia-Wei Su:
  A phase-detect synchronous mirror delay for clock skew-compensation circuits. 1070-1073
  
• I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu:
  A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. 1074-1077
  
• Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner:
  A linear model for high-level delay estimation in VDSM on-chip interconnects. 1078-1081
  
• Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam:
  A closed-form delay formula for on-chip RLC interconnects in current-mode signaling. 1082-1085
  
• Soo-Chang Pei, Meng-Ping Kao:
  Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices. 1086-1089
  
• Truong T. Nguyen, Soontorn Oraintara:
  Multidimensional filter banks design by direct optimization. 1090-1093
  
• S. C. Chan, S. S. Yin:
  On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banks. 1094-1097
  
• Robert Bregovic, Tapio Saramäki:
  Design of two-channels FIR filterbanks with rational sampling factors using the FRM technique. 1098-1101
  
• Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
  Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. 1102-1105
  
• Pilar Martín-Martín, Fernando Cruz-Roldán, Tapio Saramäki:
  : Optimized transmultiplexers for multirate systems. 1106-1109
  
• Truong T. Nguyen, Soontorn Oraintara:
  A class of directional filter banks [image processing applications]. 1110-1113
  
• Mariane R. Petraglia, Paulo B. Batalheiro:
  Filter bank design for an adaptive subband structure with critical sampling using a new adaptation scheme. 1114-1117
  
• Hau-Jie Liang, Shuenn-Shyang Wang:
  Architectural design of fractal image coder based on kick-out condition. 1118-1121
  
• Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal:
  Dictionary-based program compression on transport triggered architectures. 1122-1125
  
• Bo Fang, Guobin Shen, Shipeng Li, Huifang Chen:
  Techniques for efficient DCT/IDCT implementation on generic GPU. 1126-1129
  
• Yun Yang, Wenqing Zhao, Yasuaki Inoue:
  High-performance systolic arrays for band matrix multiplication. 1130-1133
  
• Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen:
  Block-level parallel processing for scaling evenly divisible frames. 1134-1137
  
• Daewook Kim, Manho Kim, Gerald E. Sobelman:
  Parallel FFT computation with a CDMA-based network-on-chip. 1138-1141
  
• Hongtu Jiang, Håkan Ardö, Viktor Öwall:
  Hardware accelerator design for video segmentation with multi-modal background modelling. 1142-1145
  
• Saed Samadi, M. Omair Ahmad, M. N. S. Swamy:
  Multiplier-free structures for exact generation of natural powers of integers. 1146-1149
  
• Ching-Yuan Yang, Yu Lee:
  A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. 1150-1153
  
• Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, A. Dabrowski:
  3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. 1154-1157
  
• Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang:
  A 0.18µm CMOS transceiver design for high-speed backplane data communications. 1158-1161
  
• Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue:
  A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. 1162-1165
  
• Miguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas:
  An electrically adjustable distributed pulse shaping filter for 40 Gbit/s optical links. 1166-1169
  
• Mona M. Hella, Richard Panock:
  Dual-loop control of laser drivers for 3.125GHz optical transceivers. 1170-1173
  
• Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang:
  A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. 1174-1177
  
• Vasanth Kakani, Foster F. Dai, Richard C. Jaeger:
  An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. 1178-1181
  
• Kun-Hsien Lin, Ming-Dou Ker:
  ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. 1182-1185
  
• Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu:
  A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump. 1190-1193
  
• Markus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ:
  ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies. 1194-1197
  
• Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong:
  A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. 1198-1201
  
• Elyse Rosenbaum, Sami Hyvonen:
  On-chip ESD protection for RF I/Os: devices, circuits and models. 1202-1205
  
• Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
  A methodology for partitioning DSP applications in hybrid reconfigurable systems. 1206-1209
  
• Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
  A new approach based on LFF for optimization of dynamic hardware reconfigurations. 1210-1213
  
• Minoru Watanabe, Fuminori Kobayashi:
  A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. 1214-1217
  
• Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen:
  Pipelining technique for energy-aware datapaths. 1218-1221
  
• Somsubhra Mondal, Seda Ogrenci Memik:
  A low power FPGA routing architecture. 1222-1225
  
• Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan:
  Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]. 1226-1229
  
• Zhi Zhou, Shijun Sun, Shawmin Lei, Ming-Ting Sun:
  Motion information and coding mode reuse for MPEG-2 to H.264 transcoding. 1230-1233
  
• Yeping Su, Jun Xin, Anthony Vetro, Huifang Sun:
  Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domain. 1234-1237
  
• You-Neng Xiao, Hong Lu, Xiangyang Xue, Viet Anh Nguyen, Yap-Peng Tan:
  Efficient rate control for MPEG-2 to H.264/AVC transcoding. 1238-1241
  
• Chen-Po Chang, Chia-Wen Lin:
  R-D optimized quantization of H.264 SP-frames for bitstream switching under storage constraints. 1242-1245
  
• Xiaoan Lu, Alexis Michael Tourapis, Peng Yin, Jill M. Boyce:
  Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcoding. 1246-1249
  
• Ching-Yung Lin, Belle L. Tseng:
  Optimizing user expectations for video semantic filtering and abstraction. 1250-1253
  
• Lacina M. Coulibaly, H. J. Kadim:
  Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation. 1254-1257
  
• Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang:
  An all-digital pulsewidth control loop. 1258-1261
  
• Hui Zhang, Pinaki Mazumder:
  Design of a new sense amplifier flip-flop with improved power-delay-product. 1262-1265
  
• Davide Baderna, Alessandro Cabrini, Guido De Sandre, Francesco De Santis, Marco Pasotti, Andrea Rossini, Guido Torelli:
  A 1.2 V sense amplifier for high-performance embeddable NOR flash memories. 1266-1269
  
• Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Casagrande, Roberto Gastaldi, Claudio Resta, Guido Torelli, Daniele Zella:
  SET and RESET pulse characterization in BJT-selected phase-change memories. 1270-1273
  
• Jing Chen, Miao Li, Tad A. Kwasniewski:
  Decision feedback equalization for high-speed backplane data communications. 1274-1277
  
• Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai:
  Interconnect model reductions by using the AORA algorithm with considering the adjoint network. 1278-1281
  
• Hua Tang, Alex Doboli:
  Parameter domain pruning for improving convergence of synthesis algorithms. 1282-1285
  
• Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli:
  Enriching an analog platform for analog-to-digital converter design. 1286-1289
  
• Alfred Tze-Mun Leung, Roni Khazaka:
  Parametric model order reduction technique for design optimization. 1290-1293
  
• Gülin Tulunay, Sina Balkir:
  Design automation of single-ended LNAs using symbolic analysis. 1294-1297
  
• Trent McConaghy, Georges G. E. Gielen:
  Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. 1298-1301
  
• Vahid Yousefzadeh, Eduard Alarcón, Dragan Maksimovic:
  Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers. 1302-1305
  
• Shiyan Hu, Han Huang, Dariusz Czarkowski:
  Hybrid trigonometric differential evolution for optimizing harmonic distribution. 1306-1309
  
• Boris Axelrod, Yefim Berkovich, Adrian Ioinovici:
  Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode. 1310-1313
  
• Yushan Li, Dragan Maksimovic:
  High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers. 1314-1317
  
• Carlos Meza, Domingo Biel, Luis Martinez-Salamero, Francisco Guinjoan:
  Boost-buck inverter variable structure control for grid-connected photovoltaic systems. 1318-1321
  
• Hirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori:
  Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses. 1322-1325
  
• Jingbo Yang, Meng Tong Tan, Joseph Sylvester Chang:
  Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation. 1326-1329
  
• Joachim Neves Rodrigues, Thomas Olsson, Leif Sörnmo, Viktor Öwall:
  A dual-mode wavelet based R-wave detector using single-V_t for leakage reduction [cardiac pacemaker applications]. 1330-1333
  
• Hakan Gürkan, Ümit Güz, B. Siddik Yarman:
  An efficient ECG data compression technique based on predefined signature and envelope vector banks. 1334-1337
  
• Qiyue Zou, Zhiping Lin, Raimund J. Ober:
  The CRLB for bilinear systems and its biomedical applications. 1338-1341
  
• Kyle E. Thomson, Theo Shlien, Yasir Suhail, Karim G. Oweiss:
  Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices. 1342-1345
  
• Yehya H. Ghallab, Wael M. Badawy:
  A novel CMOS lab-on-a-chip for biomedical applications. 1346-1349
  
• Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu:
  Probabilistic congestion prediction in hierarchical quad-grid model. 1350-1353
  
• Akira Matsubayashi:
  Small congestion embedding of separable graphs into grids of the same size. 1354-1357
  
• Toshinori Yamada, Hiroyuki Kawakita, Tadashi Nishiyama, Shuichi Ueno:
  On VLSI decompositions for d-ary de Bruijn graphs (extended abstract). 1358-1361
  
• Makoto Fujimoto, Daisuke Takafuji, Toshimasa Watanabe:
  Approximation algorithms for the rectilinear Steiner tree problem with obstacles. 1362-1365
  
• Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen:
  Wiring area optimization in floorplan-aware hierarchical power grids. 1366-1369
  
• Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee:
  Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. 1370-1373
  
• Jen-Lin Fan, Jieh-Tsorng Wu:
  A robust background calibration technique for switched-capacitor pipelined ADCs. 1374-1377
  
• Le Jin, Degang Chen, Randall L. Geiger:
  A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals. 1378-1381
  
• Ding-Lan Shen, Tai-Cheng Lee:
  A linear-approximation technique for digitally-calibrated pipelined A/D converters. 1382-1385
  
• Cristiano Azzolini, Andrea Boni, Alessio Facen, Matteo Parenti, Davide Vecchi:
  Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology. 1386-1389
  
• Oscar E. Agazzi, Venu Gopinathan:
  Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniques. 1390-1393
  
• Christian Vogel, Dieter Draxelmayr, Gernot Kubin:
  Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters. 1394-1397
  
• Phil Corbishley, Esther Rodríguez-Villegas:
  Programmable switched-current floating-gate cells. 1398-1401
  
• Daeik D. Kim, Martin A. Brooke:
  Time-interleaved switched-capacitor filter for reconfigurable triple-band delta-sigma converter. 1402-1405
  
• Hooman Kaabi, Mohammad-Reza Jahed Motlagh, Ahmad Ayatollahi:
  A novel current-conveyor-based switched-capacitor integrator. 1406-1408
  
• Hashem Zare-Hoseini, Omid Shoaei, Izzet Kale:
  A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch. 1409-1412
  
• Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
  Inverter-based switched current circuit for very low-voltage and low-power applications. 1413-1416
  
• Hold Omid Rajaee, Mehrdad Sharif Bakhtiar:
  A high speed, high resolution, low voltage current mode sample and hold. 1417-1420
  
• Liang Chen, Qiang Hua, H. K. Kwan:
  An improved algorithm for maximum-likelihood based approach for a multitarget tracking problem. 1421-1424
  
• Andrzej Tarczynski, Dongdong Qu:
  Optimal periodic sampling sequences for nearly-alias-free digital signal processing. 1425-1428
  
• Tuomo W. Pirinen:
  Normalized confidence factors for robust direction of arrival estimation. 1429-1432
  
• Wei Xing Zheng:
  An efficient method for estimation of autoregressive signals in noise. 1433-1436
  
• Zaihe Yu, Yun Q. Shi, Wei Su:
  Symbol-rate estimation based on filter bank. 1437-1440
  
• Nanyan Y. Wang, Panajotis Agathoklis, Andreas Antoniou:
  Pilot-aided DOA estimation for CDMA communication systems. 1441-1444
  
• Yasuhiro Takahashi, Michio Yokoyama:
  New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. 1445-1448
  
• Kenny Johansson, Oscar Gustafsson, Lars Wanhammar:
  Implementation of low-complexity FIR filters using serial arithmetic. 1449-1452
  
• Oscar Gustafsson, Henrik Ohlsson:
  A low power decimation filter architecture for high-speed single-bit sigma-delta modulation. 1453-1456
  
• Arjuna Madanayake, Leonard T. Bruton:
  A high performance distributed-parallel-processor architecture for 3D IIR digital filters. 1457-1460
  
• Chengjun Zhang, Chunyan Wang, M. Omair Ahmad:
  A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform. 1461-1464
  
• Moonseok Kang, Wonyong Sung:
  Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor. 1465-1468
  
• Dong Dai, Yue Ma, Chi K. Michael Tse:
  Horseshoes, homoclinic connections and global chaos in current-mode controlled DC/DC converters. 1469-1472
  
• Simin Yu, Jinhu Lu, Henry Leung, Guanrong Chen:
  N-scroll chaotic attractors from a general jerk circuit. 1473-1476
  
• A. Kato, T. Kohda:
  Solvable 2-dimensional rational chaotic map defined by Jacobian elliptic functions. 1477-1480
  
• Yoko Uwate, Yoshifumi Nishio:
  Back propagation learning of neural networks with chaotically-selected affordable neurons. 1481-1484
  
• Fabiola Angulo, Mario di Bernardo:
  On two-parameter non-smooth bifurcations in power converters. 1485-1488
  
• M. Balestra, Marco Lazzarini, Gianluca Setti, Riccardo Rovatti:
  Experimental performance evaluation of a low-EMI chaos-based current-programmed DC/DC boost converter. 1489-1492
  
• Chen-Fu Lin, Jin-Jang Leou:
  An adaptive fast full search motion estimation algorithm for H.264. 1493-1496
  
• Chen Chen, Ping-Hao Wu, Homer H. Chen:
  Transform-domain intra prediction for H.264. 1497-1500
  
• Minqiang Jiang, Nam Ling:
  An improved frame and macroblock layer bit allocation scheme for H.264 rate control. 1501-1504
  
• Shu-Fa Lin, Meng-Ting Lu, Ming-Yu Chen, Chia-Ho Pan:
  Fast multi-frame motion estimation for H.264 and its applications to complexity-aware streaming. 1505-1508
  
• Chao-Chung Cheng, Tian-Sheuan Chang:
  Fast three step intra prediction algorithm for 4×4 blocks in H.264. 1509-1512
  
• Chi-Wai Lam, Lai-Man Po:
  Fast block motion estimation with early acceptance technique in H.264/JVT. 1513-1516
  
• Takayuki Yamashita, Kazuhisa Haeiwa, Toshihiro Negishi, Izuru Murasaki, Yoshikazu Toba, Masatoshi Onizawa:
  Development of a microwave receiving and transmission system using an optical modulator. 1517-1520
  
• Jonathan Sewter, Anthony Chan Carusone:
  A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. 1521-1524
  
• Hai Qi Liu, Wang Ling Goh, L. Siek:
  A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers. 1525-1528
  
• Ju-Hyoung Mun, Sung Min Park, Myung-Ryong Nam:
  Four-channel CMOS photoreceiver array for parallel optical interconnects. 1529-1532
  
• Ho-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin:
  A switched delay line based optical switch architecture with a bypass line. 1533-1536
  
• Euhan Chong, Khoman Phang:
  A 400Mbps CMOS spatially-modulated photoreceiver for optical storage. 1537-1540
  
• Ka-Man Wong, Kwok-Wai Cheung, Lai-Man Po:
  MIRROR: an interactive content based image retrieval system. 1541-1544
  
• Yinqing Zhao, C. C. Jay Kuo:
  Scheduling design for distributed video-on-demand servers. 1545-1548
  
• Liuhong Liang, Hong Lu, Xiangyang Xue, Yap-Peng Tan:
  Program segmentation for TV videos. 1549-1552
  
• Huang-Chia Shih, Chung-Lin Huang:
  Content-based scalable sports video retrieval system. 1553-1556
  
• Jun-Hua Han, De-Shuang Huang:
  A novel BP-based image retrieval system. 1557-1560
  
• Vadim Ivanov, Igor M. Filanovsky:
  A 110 dB CMRR/PSRR/gain CMOS operational amplifier. 1561-1564
  
• Mohammad Yavari, Omid Shoaei, Francesco Svelto:
  Hybrid cascode compensation for two-stage CMOS operational amplifiers. 1565-1568
  
• A. D. Grasso, Salvatore Pennisi:
  High-performance CMOS pseudo-differential amplifier. 1569-1572
  
• Salvatore Pennisi:
  High-performance CMOS current feedback operational amplifier. 1573-1576
  
• Khanittha Kaewdang, Wanlop Surakampontorn, Nobuo Fujii:
  A design of controllable. 1577-1580
  
• Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
  A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. 1581-1584
  
• Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
  A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. 1585-1588
  
• Takao Tsukutani, Yasuaki Sumi, Masami Higashimura, Yutaka Fukui:
  Current-mode universal biquad circuit using MO-OTAs and DO-CCII. 1589-1592
  
• T. Halvorsrod, O. Birkenes, C. Eichrodt:
  A low-power method adding continuous variable gain to amplifiers. 1593-1596
  
• E. D. Totev, Chris J. M. Verhoeven:
  Design consideration for lowering sensitivity to out of band interference of negative feedback amplifiers. 1597-1600
  
• Yanjie Wang, Rabin Raut:
  A 2.4 GHz 82 dB-Omega fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topology. 1601-1605
  
• Apisak Worapishet, I. Roopkom:
  Cascaded double-stage configuration for high-performance broadband amplification in CMOS. 1606-1609
  
• Koen van Hartingsveldt, Chris J. M. Verhoeven, J. Willms:
  Influence of frequency compensation on the linearity of negative feedback amplifiers. 1610-1613
  
• Wacharapol Pongpalit, Varakorn Kasemsuwan, Hyung Keun Ahn:
  A 3 Gb/s 80 dB CMOS differential transimpedance amplifier for optical communication systems. 1614-1617
  
• Yu Lin, Vipul Katyal, Randall L. Geiger:
  Power dependence of feedback amplifiers on opamp architecture. 1618-1621
  
• Soliman A. Mahmoud, Mohammed A. Hashiesh, Ahmed M. Soliman:
  Digitally controlled fully differential current conveyor: CMOS realization and applications. 1622-1625
  
• Subhadeep Roy:
  A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors. 1626-1629
  
• Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan:
  A configurable dual moduli multi-operand modulo adder. 1630-1633
  
• Shahnam Khabiri, Maitham Shams:
  An MCML four-bit ripple-carry adder design in 1 GHz range. 1634-1637
  
• Ming-Chen Wen, Sying-Jyan Wang, Yen-Nan Lin:
  Low power parallel multiplier with column bypassing. 1638-1641
  
• Jieh-Hwang Yen, Lan-Rong Dung, Chi-Yuan Shen:
  Design of power-aware multiplier with graceful quality-power trade-offs. 1642-1645
  
• Xiaoyao Liang, Akshay Athalye, Sangjin Hong:
  Equalizing data-path for processing speed determination in block level pipelining. 1646-1649
  
• Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi:
  Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design. 1650-1653
  
• Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson:
  A low-leakage twin-precision multiplier using reconfigurable power gating. 1654-1657
  
• Lei Wang:
  An energy-efficient skew compensation technique for high-speed skew-sensitive signaling. 1658-1661
  
• Donald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan:
  Area, power, and pin efficient bus transceiver using multi-bit-differential signaling. 1662-1665
  
• Behnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh:
  Enhancing the efficiency of cluster voltage scaling technique for low-power application. 1666-1669
  
• Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh:
  A low-power high-SFDR CMOS direct digital frequency synthesizer. 1670-1673
  
• A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani:
  Domino logic with an efficient variable threshold voltage keeper. 1674-1677
  
• Tadayoshi Enomoto, Nobuaki Kobayashi:
  A low dynamic power and low leakage power CMOS square-root circuit. 1678-1681
  
• Jianfeng Chen, Koksoon Phua, Louis Shue, Hanwu Sun:
  A robust adaptive cross microphone array. 1682-1685
  
• Mohammed A. Khasawneh, Khaled A. Mayyas, R. M. Shalabi, Monther I. Haddad:
  A combined TDA/FDA adaptive schema for stereophonic acoustic echo cancellation. 1686-1689
  
• Rong-Jian Chen, Wen-Kai Lu, Jui-Lin Lai:
  Image encryption using progressive cellular automata substitution and SCAN. 1690-1693
  
• Wei Xing Zheng:
  Study of a least-squares type method for noisy FIR filtering. 1694-1697
  
• Isao Nakanishi, Hiroyuki Sakamoto, Yoshio Itoh, Yutaka Fukui:
  Optimal user weighting fusion in DWT domain on-line signature verification. 1698-1701
  
• Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi:
  A hardware generator for multi-point distributed random variables. 1702-1705
  
• Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takashi Katagiri:
  Direct-digital synthesis using delta-sigma modulated signals. 1706-1709
  
• Xinping Huang, Mario Caron:
  Performance of a type-based digital predistorter for solid-state power amplifier linearization. 1710-1713
  
• Hui Zhao, Kan Zheng, Wenbo Wang:
  Diversity gain's influence on MIMO's detection. 1714-1717
  
• Deepali Arora, Panajotis Agathoklis:
  Multiuser scheduling for downlink in multi-antenna wireless systems. 1718-1721
  
• Zhiguo Zhang, Shing-Chow Chan, Hui Cheng:
  Robust adaptive channel estimation of OFDM systems in time-varying narrowband interference. 1722-1725
  
• Hoang-Yang Lu, Wen-Hsien Fang:
  Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMA. 1726-1729
  
• Yu-Hao Chang, Xiaoli Yu:
  Reduced-rank antenna selection for MIMO DS-CDMA channels. 1730-1733
  
• Saman S. Abeysekera, Zhi Wang:
  Performance of the pulse pair method with an optimal lag value for frequency estimation in fading channels. 1734-1737
  
• Dae-Ik Kim, Mikkel A. Thomas, Jeffrey J. Lillie, Karla S. Dennis, Benita M. Comeau, Martin A. Brooke, Nan M. Jokerst, Stephen E. Ralph, Clifford L. Henderson:
  Integrated mixed-signal optoelectronic system-on-a-chip sensor. 1738-1741
  
• Francisco Serra-Graells, Bertrand Misischi, Eduardo Casanueva, César Méndez, Lluís Terés:
  A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors. 1742-1745
  
• Xiaolong Wu, Jian Ma, Yingtao Jiang, Bingmei Fu, Wei Hang, Jinsuo Zhang, Ning Li:
  Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutectic. 1746-1749
  
• Jianfeng Chen, Jianmin Zhang, Alvin Harvey Kam, Louis Shue:
  An automatic acoustic bathroom monitoring system. 1750-1753
  
• Yat-Fong Yung, Amine Bermak:
  A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM. 1754-1757
  
• Matti Kutila, Jouko Viitanen:
  Sensor array for multiple emission gas measurements. 1758-1761
  
• Lisa E. Hansen, Matthew M. W. Johnston, Denise M. Wilson:
  Pulse-based interface circuits for SPR sensing systems [analyte concentration measurement]. 1762-1765
  
• Christian Neeb, Michael J. Thul, Norbert Wehn:
  Network-on-chip-centric approach to interleaving in high throughput channel decoders. 1766-1769
  
• Axel Jantsch, Robert Lauter, Arseni Vitkovski:
  Power analysis of link level and end-to-end data protection in networks on chip. 1770-1773
  
• Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh:
  Effect of traffic localization on energy dissipation in NoC-based interconnect. 1774-1777
  
• Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar:
  A methodology for design, modeling, and analysis of networks-on-chip. 1778-1781
  
• Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
  Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. 1782-1785
  
• Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi:
  VLSI architecture based on packet data transfer scheme and its application. 1786-1789
  
• Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen:
  Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. 1790-1793
  
• Cao Wei, Mao Zhi Gang:
  A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264. 1794-1797
  
• Yi-Hau Chen, Ching-Yeh Chen, Liang-Gee Chen:
  Architecture of global motion compensation for MPEG-4 advanced simple profile. 1798-1801
  
• Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
  Combined 2-D transform and quantization architectures for H.264 video coders. 1802-1805
  
• Nelson Yen-Chung Chang, Tian-Sheuan Chang:
  Combined frame memory architecture for motion compensation in video decoding. 1806-1809
  
• Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee:
  An H.264/AVC decoder with 4×4-block level pipeline. 1810-1813
  
• Andrew G. Dempster, Malcolm D. Macleod:
  Multiplication by two integers using the minimum number of adders. 1814-1817
  
• Ya Jun Yu, Yong Ching Lim:
  Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks. 1819-1822
  
• Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
  I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. 1823-1826
  
• Juha Yli-Kaakinen, Tapio Saramäki:
  Design and implementation of multiplierless adjustable fractional-delay all-pass filters. 1827-1830
  
• Wu-Sheng Lu:
  Design of FIR digital filters with discrete coefficients via convex relaxation. 1831-1834
  
• Chao Cheng, Keshab K. Parhi:
  Further complexity reduction of parallel FIR filters. 1835-1838
  
• Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez:
  Glitch-free discretely programmable clock generation on chip. 1839-1842
  
• Yan Zhang, Travis N. Blalock, Mircea R. Stan:
  A three-level toggle-avoid bus signaling scheme. 1843-1846
  
• Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun:
  A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. 1847-1850
  
• Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias:
  A distributed FIFO scheme for on chip communication. 1851-1854
  
• Jan Doutreloigne, Miguel Vermandel, Herbert De Smet, André Van Calster:
  A multifunctional high-voltage driver chip for low-power mobile display systems. 1855-1858
  
• Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
  Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. 1859-1862
  
• Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
  Performance constrained floorplanning based on partial clustering [IC layout]. 1863-1866
  
• Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee:
  Wire-driven microarchitectural design space exploration. 1867-1870
  
• Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
  Integrated routing resource assignment for RLC crosstalk minimization. 1871-1874
  
• Yen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh:
  Placement for the reconfigurable datapath architecture. 1875-1878
  
• Hao-Yueh Hsieh, Ting-Chi Wang:
  Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. 1879-1882
  
• Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani:
  Fixed-outline floorplanning with constraints through instance augmentation. 1883-1886
  
• Christian Falconi, Giancarlo Savone, Arnaldo D'Amico:
  High light-load efficiency charge pumps. 1887-1890
  
• Davide Baderna, Alessandro Cabrini, Guido Torelli, Marco Pasotti:
  Efficiency comparison between doubler and Dickson charge pumps. 1891-1894
  
• Wing-Hung Ki, Feng Su, Chi-Ying Tsui:
  Charge redistribution loss consideration in optimal charge pump design. 1895-1898
  
• T. Hasan, Torsten Lehmann, Chee Yee Kwok:
  A 5V charge pump in a standard 1.8-V 0.18-µm CMOS process. 1899-1902
  
• R. Arona, Edoardo Bonizzoni, Franco Maloberti, Guido Torelli:
  Heap charge pump optimisation by a tapered architecture. 1903-1906
  
• Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
  Gate control strategies for high efficiency charge pumps. 1907-1910