ISLPED 1997: Monterey, California, USA
Brock Barton, Massoud Pedram, Anantha Chandrakasan, Sayfe Kiaei (Eds.): Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997, Monterey, California, USA, August 18-20, 1997. ACM 1997 ISBN 0-89791-903-3- June Jiang, Kan Lu, Uming Ko: High-performance, low-power design techniques for dynamic to static logic interface. 12-17
- Dinesh Somasekhar, Kaushik Roy: LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. 18-23
- Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer: System-level power optimization of special purpose applications: the beach solution. 24-29
- Jean-Philippe Diguet, Sven Wuytack, Francky Catthoor, Hugo De Man: Formalized methodology for data reuse exploration in hierarchical memory mappings. 30-35
- Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka: A low-power design method using multiple supply voltages. 36-41
- Sven Mattisson: Minimizing power dissipation of cellular phones. 42-45
- Donald A. Hitko, Theodore L. Tewksbury, Charles Sodini: A 1V, 5mW, 1.8GHz balanced voltage-controlled oscillator with an integrated resonator. 46-51
- Mats Erling Høvin, S. Kiaei, Tor Sverre Lande: Delta Sigma frequency-to-time conversion by triangularly weighted ZC counter. 52-55
- Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi: A symbolic algorithm for low-power sequential synthesis. 56-61
- Emad N. Farag, Ran-Hong Yan, Mohamed I. Elmasry: A programmable power-efficient decimation filter for software radios. 68-71
- Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh: Techniques for low energy software. 72-75
- Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa: Low-power H.263 video CoDec dedicated to mobile computing. 80-83
- Jason J. Brown, Danny Z. Chen, Garrison W. Greenwood, Xiaobo Hu, Richard W. Taylor: Scheduling for power reduction in a real-time system. 84-87
- Premal Buch, Christopher K. Lennard, A. Richard Newton: Engineering change for power optimization using global sensitivity and synthesis flexibility. 88-91
- Steven M. Nowick, Michael Theobald: Synthesis of low-power asynchronous circuits in a specified environment. 92-95
- Yibin Ye, Kaushik Roy, Georgios I. Stamoulis: Quasi-static energy recovery logic and supply-clock generation circuits. 96-99
- Bum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim: A new 4-2 adder and booth selector for low power MAC unit. 100-103
- A. Schlaffer, Josef A. Nossek: Enhanced prediction of energy losses during adiabatic charging. 104-107
- J. Zhou, R. M. Ziazadeh, H.-H. Ng, H.-T. Ng, David J. Allstot: Charge-pump assisted low-power/low-voltage CMOS opamp design. 108-109
- J. A. E. P. van Engelen, Rudy J. van de Plassche: New stability criteria for the design of low-pass sigma-delta modulators. 114-118
- Lapoe Lynn, Paul Ferguson Jr.: A capacitor-based D/A converter with continuous time output for low-power applications. 119-124
- Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding: Cycle-accurate macro-models for RT-level power analysis. 125-130
- Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, Takashi Kambe: A method of redundant clocking detection and power reduction at RT level design. 131-136
- R. S. Bajwa, N. Schumann, H. Kojima: Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP. 137-142
- James D. Meindl: A history of low power electronics: how it began and where it's headed. 149-151
- Jerry Frenkil: Issues and directions in low power design tools: an industrial perspective. 152-157
- Jan M. Rabaey: System-level power estimation and optimization - challenges and perspectives. 158-160
- Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. 161-166
- Zhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou: Low power motion estimation design using adaptive pixel truncation. 167-172
- Michael J. Dong, K. Geoffrey Yung, William J. Kaiser: Low power signal processing architectures for network microsensors. 173-177
- Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: K2: an estimator for peak sustainable power of VLSI circuits. 178-183
- José C. Costa, José C. Monteiro, Srinivas Devadas: Switching activity estimation using limited depth reconvergent path analysis. 184-189
- Radu Marculescu, Diana Marculescu, Massoud Pedram: Composite sequence compaction for finite-state machines using block entropy and high-order Markov models. 190-195
- Enric Musoll, Tomás Lang, Jordi Cortadella: Exploiting the locality of memory references to reduce the address bus energy. 202-207
- Rafael Fried: Minimizing energy dissipation in high-speed multipliers. 214-219
- Hyung-Joon Kwon, Kwyro Lee: A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications. 220-224
- David Garrett, Mircea R. Stan: Power reduction techniques for a spread spectrum based correlator. 225-230
- Li-Pen Yuan, Sung-Mo Kang: A sequential procedure for average power analysis of sequential circuits. 231-234
- R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. 235-238
- Patrick Hicks, Matthew Walnock, Robert Michael Owens: Analysis of power consumption in memory hierarchies. 239-242
- Ying-Che Tseng, Steven C. Chin, Jason C. S. Woo: The impact of SOI MOSFETs on low power digital circuits. 243-246
- Wei Jin, Philip C. H. Chan, Mansun Chan: On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter. 247-250
- Markku Åberg, Anssi Leppänen, Arto Rantala, Jouko Marjonen: Analogue LSI RF switch and beamforming matrixes for communications satellites. 251-254
- Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba: Low power architecture for high speed infrared wireless communication system. 255-258
- Mir Azam, Paul D. Franzon, Wentai Liu: Low power data processing by elimination of redundant computations. 259-264
- Yukihiro Yoshida, Bao-Yu Song, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa: An object code compression approach to embedded processors. 265-268
- Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu: Low power multiplexer decomposition. 269-274
- Winfried Nöth, Reiner Kolla: Node normalization and decomposition in low power technology mapping. 275-280
- Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A gate resizing technique for high reduction in power consumption. 281-286
- Patrick Vuillod, Luca Benini, Giovanni De Micheli: Re-mapping for low power under tight timing constraints. 287-292
- Jim Burr, Anantha Chandrakasan, Fari Assaderaghi, Francky Catthoor, Frank Fox, Dave Greenhill, Deo Singh, Jim Sproch: Low power design without compromise (panel). 293-294
- Dimitri A. Antoniadis: SOI CMOS as a mainstream low power technology: a critical assessment. 295-300
- Srinivasa R. Banna, Philip C. H. Chan, Mansun Chan, Samuel K. H. Fung, Ping K. Ko: Fully depleted CMOS/SOI device design guidelines for low power applications. 301-306
- Uming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava: Hybrid dual-threshold design techniques for high-performance processors with low-power features. 307-311
- Kai Chen, Chenming Hu: Device and technology optimizations for low power design in deep sub-micron regime. 312-316
- David J. Frank, Paul Solomon, Scott K. Reynolds, John Shin: Supply and threshold voltage optimization for low power design. 317-322
- Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. 323-327
- William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W.-C. Liu: AC-1: a clock-powered microprocessor. 328-333
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