ISLPED 1999: San Diego, California, USA

• Asad A. Abidi, Houshang Darabi:
  Low power RF integrated circuits: principles and practice. 1-6
  
• Finn Müller, Nikolai Bisgaard, John Melanson:
  Algorithm and architecture of a 1V low power hearing instrument DSP. 7-11
  
• Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka:
  A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. 12-17
  
• Nestoras Tzartzanis, William C. Athas:
  Retractile clock-powered logic. 18-23
  
• Ganesh Balamurugan, Naresh R. Shanbhag:
  Energy-efficient dynamic circuit design in the presence of crosstalk noise. 24-29
  
• Rajamohana Hegde, Naresh R. Shanbhag:
  Energy-efficient signal processing via algorithmic noise-tolerance. 30-35
  
• Oliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng:
  Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. 36-41
  
• Christopher Deng, Charles Chien:
  A low energy architecture for fast PN acquisition. 42-47
  
• Scott Meninger, Jose Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha Chandrakasan, Jeffrey Lang:
  Vibration-to-electric energy conversion. 48-53
  
• Fuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru Furuyama:
  Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec. 54-59
  
• Vladimir Koifman, Yachin Afek, Joseph Shor:
  Circuit methods for the integration of low voltage (1.1-1.8V) analog functions on system-on-a-chip IC's in a single-poly CMOS processes. 60-63
  
• Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
  Using dynamic cache management techniques to reduce energy in a high-performance processor. 64-69
  
• Kanad Ghose, Milind B. Kamble:
  Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. 70-75
  
• Curt Schurgers, Francky Catthoor, Marc Engels:
  Energy efficient data transfer and storage organization for a MAP turbo decoder module. 76-81
  
• Bharath Ramasubramanian, Herman Schmit, L. Richard Carley:
  Mixed-swing quadrail for low power dual-rail domino logic. 82-84
  
• Benjamin Bishop, Mary Jane Irwin:
  Databus charge recovery: practical considerations. 85-87
  
• You-Sung Chang, Bong-Il Park, Chong-Min Kyung:
  Conforming inverted data store for low power memory. 91-93
  
• Hendrawan Soeleman, Kaushik Roy:
  Ultra-low power digital subthreshold logic circuits. 94-96
  
• Suhwan Kim, Marios C. Papaefthymiou:
  Single-phase source-coupled adiabatic logic. 97-99
  
• Yumin Zhang, Xiaobo Hu, Danny Z. Chen:
  Global register allocation for minimizing energy consumption. 100-102
  
• Subodh Gupta, Farid N. Najm:
  Power macro-models for DSP blocks with application to high-level synthesis. 103-105
  
• L. Richard Carley, Akshay Aggarwal:
  A completey on-chip voltage regulation technique for low power digital circuits. 109-111
  
• Christoph Schwoerer, Dominique Morche, Patrice Senn:
  Comparison of class A amplifiers for low-power and low-voltage switched capacitor applications. 112-114
  
• Lars Kruse, Eike Schmidt, Gerd Jochens, Wolfgang Nebel:
  Lower and upper bounds on the switching activity in scheduled data flow graphs. 115-120
  
• Subodh Gupta, Farid N. Najm:
  Energy-per-cycle estimation at RTL. 121-126
  
• Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli:
  Efficient switching activity computation during high-level synthesis of control-dominated designs. 127-132
  
• Radu Marculescu, Diana Marculescu, Massoud Pedram:
  Non-stationary effects in trace-driven power analysis. 133-138
  
• Vijay Sundararajan, Keshab K. Parhi:
  Low power synthesis of dual threshold voltage CMOS VLSI circuits. 139-144
  
• Jatuchai Pangjun, Sachin S. Sapatnekar:
  Clock distribution using multiple voltages. 145-150
  
• Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng:
  VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. 156-161
  
• Vivek De, Shekhar Borkar:
  Technology and design challenges for low power and high performance. 163-168
  
• Rajeevan Amirtharajah, Thucydides Xanthopoulos, Anantha Chandrakasan:
  Power scalable processing using distributed arithmetic. 170-175
  
• David Garrett, Mircea R. Stan, Alvar Dean:
  Challenges in clockgating for a low power ASIC methodology. 176-181
  
• William E. Dougherty, Donald E. Thomas:
  Modeling and automating selection of guarding techniques for datapath elements. 182-187
  
• George Varghese, Hui Zhang, Jan M. Rabaey:
  The design of a low energy FPGA. 188-193
  
• Qinru Qiu, Qing Wu, Massoud Pedram:
  Stochastic modeling of a power-managed system: construction and optimization. 194-199
  
• Thomas L. Martin, Daniel P. Siewiorek:
  The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study. 200-205
  
• Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  Selective instruction compression for memory energy reduction in embedded systems. 206-211
  
• Tajana Simunic, Luca Benini, Giovanni De Micheli:
  Energy-efficient design of battery-powered embedded systems. 212-217
  
• Ruchir Puri, Ching-Te Chuang:
  Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. 223-228
  
• Thierry Melly, Alain-Serge Porret, Christian C. Enz, M. Kayal, Eric A. Vittoz:
  A 1.2V, 430MHz, 4dBm power amplifier and a 250muW front-end, using a standard digital CMOS process. 233-237
  
• Razieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser:
  CMOS front-end LNA-mixer of micropower RF wireless systems. 238-242
  
• Ayman ElSayed, Akbar Ali, Mohamed I. Elmasry:
  Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump. 243-248
  
• Samuel B. Schaevitz, Christopher Lin:
  Passive precharge and rippled power logic (PPRPL). 249-251
  
• Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De:
  Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. 252-254
  
• Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari:
  An architectural solution for the inductive noise problem due to clock-gating. 255-257
  
• Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
  An optimization technique for dual-output domino logic. 258-260
  
• Peter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim:
  Statistically optimized asynchronous barrel shifters for variable length codecs. 261-263
  
• Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley:
  Inverse polarity techniques for high-speed/low-power multipliers. 264-266
  
• Lea Hwang Lee, Bill Moyer, John Arends:
  Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. 267-269
  
• Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
  A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. 270-272
  
• Koji Inoue, Tohru Ishihara, Kazuaki Murakami:
  Way-predicting set-associative cache for high performance and low energy consumption. 273-275
  
• Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith:
  Designing power efficient hypermedia processors. 276-278
  
• HoonSang Jin, Myung-Soo Jang, Jin-Suk Song, Jin-Yong Lee, Taek-Soo Kim, Jeong-Taek Kong:
  Dynamic power estimation using the probabilistic contribution measure (PCM). 279-281
  
• Fari Assaderaghi:
  Circuit styles and strategies for CMOS VLSI design on SOI. 282-287
  
• Luca Benini, Giovanni De Micheli:
  System-level power optimization: techniques and tools. 288-293
  

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