ISLPED 2002: Monterey, California, USA
Vivek De, Mary Jane Irwin, Ingrid Verbauwhede, Christian Piguet (Eds.): Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002. ACM 2002 ISBN 1-58113-475-4- Kiyoo Itoh: Low-voltage memories for power-aware systems. 1-6
- Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci: Standby power management for a 0.18µm microprocessor. 7-12
- Hyunsik Im: Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model). 13-18
- Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan: Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. 19-23
- Koichi Nose, Takayasu Sakurai: Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. 24-29
- Vijay Raghunathan, Saurabh Ganeriwal, Curt Schurgers, Mani B. Srivastava: E2WFQ: an energy efficient fair scheduling policy for wireless systems. 30-35
- Rex Min, Anantha Chandrakasan: A framework for energy-scalable communication in high-density wireless networks. 36-41
- Eui-Young Chung, Giovanni De Micheli, Luca Benini: Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. 42-47
- Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark: Managing leakage for transient data: decay and quasi-static 4T memory cells. 52-55
- Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija: Conditional pre-charge techniques for power-efficient dual-edge clocking. 56-59
- Fatih Hamzaoglu, Mircea R. Stan: Circuit-level techniques to control gate leakage for sub-100nm CMOS. 60-63
- Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. 64-67
- Rusell E. Henning, Chaitali Chakrabarti: Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations. 68-71
- Morteza Maleki, Karthik Dantu, Massoud Pedram: Power-aware source routing protocol for mobile ad hoc networks. 72-75
- Edgar G. Daylight, Sven Wuytack, Chantal Ykman-Couvreur, Francky Catthoor: Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures. 76-79
- Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan: Odd/even bus invert with two-phase transfer for buses with coupling. 80-83
- Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo: An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. 84-87
- Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura: Reducing access energy of on-chip data memory considering active data bitwidth. 88-91
- Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen: Closed-loop adaptive voltage scaling controller for standard-cell ASICs. 103-107
- Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig, Gerhard Hellner: Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. 108-111
- Inseok Choi, Hojun Shim, Naehyuck Chang: Low-power color TFT LCD display for hand-held embedded systems. 112-117
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Discharge current steering for battery lifetime optimization. 118-123
- Osman S. Unsal, Israel Koren, C. Mani Krishna: Towards energy-aware software-based fault tolerance in real-time systems. 124-129
- Aristides Efthymiou, Jim D. Garside: An adaptive serial-parallel CAM architecture for low-power cache blocks. 136-141
- Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. 142-147
- Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. 148-153
- Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach: Battery lifetime prediction for energy-aware computing. 154-159
- Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh: Early evaluation techniques for low power binding. 160-165
- Victor V. Zyuban, Philip N. Strenski: Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. 166-171
- Mark S. Lundstrom: Is nanoelectronics the future of microelectronics? 172-177
- Tejas Karkhanis, James E. Smith, Pradip Bose: Saving energy with just in time instruction delivery. 178-183
- Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster: Tradeoffs in power-efficient issue queue design. 184-189
- Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah: Reducing transitions on memory buses using sector-based encoding technique. 190-195
- Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa: Automated selective multi-threshold design for ultra-low standby applications. 202-206
- Kyu-won Choi, Abhijit Chatterjee: HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. 207-212
- Afshin Abdollahi, Massoud Pedram, Farzan Fallah: Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2. 213-218
- Ulrich Kremer: Compilers for power and energy management. 220
- Omid Oliaei: Oversampled gain-boosting. 221-226
- Simon C. Li, Jimmy C. Cha: ±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme. 227-232
- Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim: A power and resolution adaptive flash analog-to-digital converter. 233-236
- Carl De Ranter, Michiel Steyaert: Design techniques for low power high bandwidth upconversion in CMOS. 237-242
- Magnus Ekman, Per Stenström, Fredrik Dahlgren: TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. 243-246
- Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada: A preactivating mechanism for a VT-CMOS cache using address prediction. 247-250
- Chris H. Kim, Kaushik Roy: Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. 251-254
- Amirali Baniasadi, Andreas Moshovos: Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. 255-258
- Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: Power analysis techniques for SoC with improved wiring models. 259-262
- Wael El-Essawy, David H. Albonesi, Balaram Sinharoy: A microarchitectural-level step-power analysis tool. 263-266
- Ashok K. Murugavel, N. Ranganathan: Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. 267-270
- Chunhong Chen, Changjun Kang, Majid Sarrafzadeh: Activity-sensitive clock tree construction for low power. 279-282
- Mohammad M. Mansour, Naresh R. Shanbhag: Low-power VLSI decoder architectures for LDPC codes. 284-289
- David Garrett, Chris Nicol, Andrew J. Blanksby, Chris Howland: A low power normalized-LMS decision feedback equalizer for a wireless packet modem. 290-294
- Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy: High performance and low power FIR filter design based on sharing multiplication. 295-300
- Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura: A low-power digital matched filter for spread-spectrum systems. 301-306
- Davide Bertozzi, Luca Benini, Bruno Riccò: Parametric timing and power macromodels for high level simulation of low-swing interconnects. 307-312
- William C. Athas, Lynn Youngs, Andrew Reinhart: Compact models for estimating microprocessor frequency and power. 313-318
- Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner: Efficient estimation of signal transition activity in MAC architectures. 319-322
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last updated on 2013-06-19T203413 by the dblp team