ISLPED 2005: San Diego, California, USA

• Dennis Buss:
  Technology and design challenges for mobile communication and computing products. 1
  

Technologies and devices for low power

• Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic:
  FinFET-based SRAM design. 2-7
  
• Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy:
  Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. 8-13
  
• Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy:
  Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations. 14-19
  
• Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester:
  Analysis and mitigation of variability in subthreshold design. 20-25
  
• Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
  Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. 26-29
  

Micro-architectural techniques

• Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin:
  Instruction packing: reducing power and delay of the dynamic scheduling logic. 30-35
  
• Ahmad Zmily, Christos Kozyrakis:
  Energy-efficient and high-performance instruction fetch using a block-aware ISA. 36-41
  
• Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang:
  Energy-aware fetch mechanism: trace cache and BTB customization. 42-47
  
• Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir:
  Understanding the energy efficiency of SMT and CMP with multiclustering. 48-53
  
• Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas:
  A simple mechanism to adapt leakage-control policies to temperature. 54-59
  

Converter and communication circuits

• Emmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin:
  A 120nm low power asynchronous ADC. 60-65
  
• Xinhua Chen, Qiuting Huang:
  A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS. 66-71
  
• Douglas Mercer:
  A low power current steering digital to analog converter in 0.18 Micron CMOS. 72-77
  
• Peter C. S. Scholtens, David Smola, Maarten Vertregt:
  Systematic power reduction and performance analysis of mismatch limited ADC designs. 78-83
  
• Lucas Andrew Milner, Gabriel A. Rincón-Mora:
  A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications. 84-89
  

Low power design for FPGAs

• Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton:
  Challenges and opportunities for low power FPGAs in nanometer technologies. 90
  

Low-power circuit techniques

• Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
  A GHz-class charge recovery logic. 91-94
  
• Behnam Amelifard, Farzan Fallah, Massoud Pedram:
  Low-power fanout optimization using multiple threshold voltage inverters. 95-98
  
• Srinivasa R. Sridhara, Naresh R. Shanbhag:
  A low-power bus design using joint repeater insertion and coding. 99-102
  
• Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar:
  An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. 103-106
  
• Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
  A low-power, multichannel gated oscillator-based CDR for short-haul applications. 107-110
  

Logic and microarchitecture

• Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri:
  An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. 111-114
  
• Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
  Cascaded carry-select adder (C²SA): a new structure for low-power CSA design. 115-118
  
• Xueqi Cheng, Michael S. Hsiao:
  Region-level approximate computation reuse for power reduction in multimedia applications. 119-122
  
• Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
  Joint exploration of architectural and physical design spaces with thermal consideration. 123-126
  
• Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark:
  Coordinated, distributed, formal energy management of chip multiprocessors. 127-130
  

Circuit-level optimizations

• Vineet Wason, Kaustav Banerjee:
  A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. 131-136
  
• Yu Ching Chang, King Ho Tam, Lei He:
  Power-optimal repeater insertion considering Vdd and Vth as design freedoms. 137-142
  
• Azadeh Davoodi, Ankur Srivastava:
  Probabilistic dual-Vth leakage optimization under variability. 143-148
  
• David G. Chinnery, Kurt Keutzer:
  Linear programming for sizing, V_th and V_dd assignment. 149-154
  

Special purpose processing

• Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo:
  An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. 155-160
  
• Marco Lanuzza, Martin Margala, Pasquale Corsonello:
  Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. 161-166
  
• Il-soo Lee, Tony Ambler:
  Two efficient methods to reduce power and testing time. 167-172
  
• Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron:
  Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. 173-178
  

Circuit techniques for scaled technologies

• Seokkee Kim, Soo-Ik Chae:
  Complexity reduction in an nRERL microprocessor. 180-185
  
• Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
  Driver pre-emphasis techniques for on-chip global buses. 186-191
  
• Jie Gu, Chris H. Kim:
  Multi-story power delivery for supply noise reduction and low voltage operation. 192-197
  
• Rabiul Islam, Adam Brand, Dave Lippincott:
  Low power SRAM techniques for handheld products. 198-202
  
• Masaya Sumita:
  High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar. 203-208
  

Low power software design and sensing

• Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen:
  An evaluation of code and data optimizations in the context of disk power reduction. 209-214
  
• Guiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Thomas F. La Porta:
  Optimizing sensor movement planning for energy efficiency. 215-220
  
• Gilberto Contreras, Margaret Martonosi:
  Power prediction for intel XScale processors using performance monitoring unit events. 221-226
  
• William R. Dieter, Srabosti Datta, Wong Key Kai:
  Power reduction by varying sampling rate. 227-232
  
• Ali Iranli, Morteza Maleki, Massoud Pedram:
  Energy efficient strategies for deployment of a two-level wireless sensor network. 233-238
  

Power grid, thermal, and leakage issues

• Maha Nizam, Farid N. Najm, Anirudh Devgan:
  Power grid voltage integrity verification. 239-244
  
• Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan:
  The need for a full-chip and package thermal model for thermally optimized IC designs. 245-250
  
• Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik:
  Peak temperature control and leakage reduction during binding in high level synthesis. 251-256
  
• Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
  LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. 257-262
  
• Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
  Defocus-aware leakage estimation and control. 263-268
  

Power management and voltage scaling

• Peng Rong, Massoud Pedram:
  Hierarchical power management with application to scheduling. 269-274
  
• W. L. Bircher, M. Valluri, J. Law, L. K. John:
  Runtime identification of microprocessor energy saving opportunities. 275-280
  
• Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger:
  Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. 281-286
  
• Fen Xie, Margaret Martonosi, Sharad Malik:
  Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. 287-292
  
• Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir:
  Power-aware code scheduling for clusters of active disks. 293-298
  

• Chandra Narayanaswami:
  Wearable computing: a catalyst for business and entertainment. 302
  

Posters: Power supply design

• Dongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu:
  Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes. 303-306
  
• Farhan Simjee, Pai H. Chou:
  Accurate battery lifetime estimation using high-frequency power profile emulation. 307-310
  
• Maurice Meijer, José Pineda de Gyvez, Ralph Otten:
  On-chip digital power supply control for system-on-chip applications. 311-314
  
• Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah:
  Self-timed circuits for energy harvesting AC power supplies. 315-318
  

Posters: I/O and memory system design

• Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar:
  A tunable bus encoder for off-chip data buses. 319-322
  
• Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
  Fast configurable-cache tuning with a unified second-level cache. 323-326
  
• Guangyu Chen, Mahmut T. Kandemir:
  Dataflow analysis for energy-efficient scratch-pad memory management. 327-330
  
• Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
  Energy reduction in multiprocessor systems using transactional memory. 331-334
  
• Jerry Hom, Ulrich Kremer:
  Inter-program optimizations for conserving disk energy. 335-338
  

Low power memory

• Yao Guo, Mahmoud Ben Naser, Csaba Andras Moritz:
  PARE: a power-aware hardware data prefetching engine. 339-344
  
• Jia-Jhe Li, Yuan-Shin Hwang:
  Snug set-associative caches: reducing leakage power while improving performance. 345-350
  
• Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao:
  An energy efficient TLB design methodology. 351-356
  
• Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic:
  Synonymous address compaction for energy reduction in data TLB. 357-362
  
• Tohru Ishihara, Farzan Fallah:
  A non-uniform cache architecture for low power system design. 363-368
  

System design methodology

• Seongmoo Heo, Krste Asanovic:
  Replacing global wires with an on-chip network: a power analysis. 369-374
  
• Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
  A low-power crossroad switch architecture and its core placement for network-on-chip. 375-380
  
• Koushik Niyogi, Diana Marculescu:
  System level power and performance modeling of GALS point-to-point communication interfaces. 381-386
  
• Krishnan Srinivasan, Karam S. Chatha:
  A technique for low energy mapping and routing in network-on-chip architectures. 387-392
  
• Hai Huang, Kang G. Shin, Charles Lefurgy, Tom W. Keller:
  Improving energy efficiency by making DRAM less randomly accessed. 393-398
  

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