San Diego, California, USA Kaushik Roy, Vivek Tiwari (Eds.):
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005.
ACM 2005, ISBN 1-59593-137-6
- Dennis Buss:
Technology and design challenges for mobile communication and computing products.
Technologies and devices for low power
- Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic:
FinFET-based SRAM design.
- Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy:
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
- Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy:
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.
- Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester:
Analysis and mitigation of variability in subthreshold design.
- Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.
- Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin:
Instruction packing: reducing power and delay of the dynamic scheduling logic.
- Ahmad Zmily, Christos Kozyrakis:
Energy-efficient and high-performance instruction fetch using a block-aware ISA.
- Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang:
Energy-aware fetch mechanism: trace cache and BTB customization.
- Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir:
Understanding the energy efficiency of SMT and CMP with multiclustering.
- Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas:
A simple mechanism to adapt leakage-control policies to temperature.
Converter and communication circuits
Low power design for FPGAs
Low-power circuit techniques
- Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
A GHz-class charge recovery logic.
- Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Low-power fanout optimization using multiple threshold voltage inverters.
- Srinivasa R. Sridhara, Naresh R. Shanbhag:
A low-power bus design using joint repeater insertion and coding.
- Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
- Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
A low-power, multichannel gated oscillator-based CDR for short-haul applications.
Logic and microarchitecture
- Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri:
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.
- Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
- Xueqi Cheng, Michael S. Hsiao:
Region-level approximate computation reuse for power reduction in multimedia applications.
- Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration.
- Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark:
Coordinated, distributed, formal energy management of chip multiprocessors.
Special purpose processing
- Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo:
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.
- Marco Lanuzza, Martin Margala, Pasquale Corsonello:
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
- Il-soo Lee, Tony Ambler:
Two efficient methods to reduce power and testing time.
- Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron:
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.
Circuit techniques for scaled technologies
Low power software design and sensing
- Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen:
An evaluation of code and data optimizations in the context of disk power reduction.
- Guiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Thomas F. La Porta:
Optimizing sensor movement planning for energy efficiency.
- Gilberto Contreras, Margaret Martonosi:
Power prediction for intel XScale processors using performance monitoring unit events.
- William R. Dieter, Srabosti Datta, Wong Key Kai:
Power reduction by varying sampling rate.
- Ali Iranli, Morteza Maleki, Massoud Pedram:
Energy efficient strategies for deployment of a two-level wireless sensor network.
Power grid, thermal, and leakage issues
- Maha Nizam, Farid N. Najm, Anirudh Devgan:
Power grid voltage integrity verification.
- Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan:
The need for a full-chip and package thermal model for thermally optimized IC designs.
- Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik:
Peak temperature control and leakage reduction during binding in high level synthesis.
- Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.
- Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
Defocus-aware leakage estimation and control.
Power management and voltage scaling
- Peng Rong, Massoud Pedram:
Hierarchical power management with application to scheduling.
- W. L. Bircher, M. Valluri, J. Law, L. K. John:
Runtime identification of microprocessor energy saving opportunities.
- Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger:
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
- Fen Xie, Margaret Martonosi, Sharad Malik:
Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation.
- Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir:
Power-aware code scheduling for clusters of active disks.
Power supply design
I/O and memory system design
Low power memory
System design methodology
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