• 
  Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle (Eds.): Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008. ACM 2008 ISBN 978-1-60558-109-5
• 
  Jaswinder Ahuja: Towards a green electronic world: a collaborative approach. 1-2

Variation tolerant circuits

• 
  Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. 3-8
• 
  Mingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. 9-14
• 
  Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara: Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. 15-20
• 
  Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim: Enhancing beneficial jitter using phase-shifted clock distribution. 21-26

Power optimization

• 
  Hao Xu, Ranga Vemuri, Wen-Ben Jone: Dynamic virtual ground voltage estimation for power gating. 27-32
• 
  Mohammad Ghasemazar, Behnam Amelifard, Massoud Pedram: A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops. 33-38
• 
  Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin: Power-gating-aware high-level synthesis. 39-44
• 
  Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi: A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. 45-50
• 
  Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. 51-56

Power delivery and timing

• 
  Pulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim: A multi-story power delivery technique for 3D integrated circuits. 57-62
• 
  Nathaniel J. Guilar, Erin G. Fong, Travis Kleeburg, Diego R. Yankelevich, Rajeevan Amirtharajah: Energy harvesting photodiodes with integrated 2D diffractive storage capacitance. 63-68
• 
  Charbel J. Akl, Magdy A. Bayoumi: Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion. 69-74
• 
  Thomas Schmid, Jonathan Friedman, Zainul Charbiwala, Young H. Cho, Mani B. Srivastava: Low-power high-accuracy timing systems for efficient duty cycling. 75-80

Variability-aware optimization

• 
  Upavan Gupta, Nagarajan Ranganathan: An expected-utility based approach to variation aware VLSI optimization under scarce information. 81-86
• 
  Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif: SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. 87-92
• 
  Maziar Goudarzi, Tohru Ishihara: Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. 93-98
• 
  Koustav Bhattacharya, Nagarajan Ranganathan: Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. 99-104
• 
  Cheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. 105-110

Low voltage logic and memory

• 
  Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders. 111-116
• 
  Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Increasing minimum operating voltage (V_DDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. 117-122
• 
  Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy: Thermal analysis of 8-T SRAM for nano-scaled technologies. 123-128
• 
  Jiajing Wang, Satyanand Nalam, Benton H. Calhoun: Analyzing static and dynamic write margin for nanometer SRAMs. 129-134

Tutorials

• 
  Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan Rubio, Heather Hanson, Tom W. Keller: Power management solutions for computer systems and datacenters. 135-136
• 
  Swarup Bhunia, Kaushik Roy: Low power design under parameter variations. 137-138

Panel

• 
  Parthasarathy Ranganathan: Power management from cores to datacenters: where are we going to get the next ten-fold improvements? 139-140

Adaptive algorithms for energy-efficient applications

• 
  Feng Chen, Xiaodong Zhang: Caching for bursts (C-Burst): let hard disks sleep well and work energetically. 141-146
• 
  Muhammad Shafique, Lars Bauer, Jörg Henkel: 3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. 147-152
• 
  Karthik Kumar, Yamini Nimmagadda, Yu-Ju Hong, Yung-Hsiang Lu: Energy conservation by adaptive feature loading for mobile content-based image retrieval. 153-158
• 
  Younghyun Kim, Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Nam Ik Cho: Extending the lifetime of media recorders constrained by battery and flash memory size. 159-164

Multi-core power optimization

• 
  Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross: Proactive temperature management in MPSoCs. 165-170
• 
  Dongwook Lee, Sungjoo Yoo, Kiyoung Choi: Entry control in network-on-chip for memory power reduction. 171-176
• 
  Suman Kalyan Mandal, Rabi N. Mahapatra: PowerAntz: distributed power sharing strategy for network on chip. 177-182
• 
  Norman P. Jouppi: System implications of integrated photonics. 183-184

Poster session

• 
  Behnam Ghavami, Hossein Pedram: Design of dual threshold voltages asynchronous circuits. 185-188
• 
  Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy: O²C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. 189-192
• 
  Shagun Bajoria, Vineet Kumar Singh, Raju Kunde, Chetan D. Parikh: Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation. 193-196
• 
  Yu-Shiang Lin, Dennis Sylvester: Single stage static level shifter design for subthreshold to I/O voltage conversion. 197-200
• 
  Arvind Madan, Bharadwaj Amrutur: Power reduction in on-chip interconnection network by serialization. 201-204
• 
  Shaobo Liu, Qinru Qiu, Qing Wu: A probabilistic technique for full-chip leakage estimation. 205-208
• 
  Jingyi Zhang, Qing Wu, Qinru Qiu: Bus encoding for simultaneous delay and energy optimization. 209-212
• 
  Michael Kadin, Sherief Reda: Frequency planning for multi-core processors under thermal constraints. 213-216
• 
  Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. 217-220
• 
  Niklas Lotze, Maurits Ortmanns, Yiannos Manoli: Variability of flip-flop timing at sub-threshold voltages. 221-224
• 
  Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma: Low power current mode receiver with inductive input impedance. 225-228
• 
  Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski: Analytical results for design space exploration of multi-core processors employing thread migration. 229-232
• 
  Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical level study and optimization of CAM-based checkpointed register alias table. 233-236

Tutorials

• 
  Vishwani D. Agrawal: A tutorial on test power. 237-238
• 
  Srikanth Balasubramanian: Power delivery for high performance microprocessors. 239-240

Memory systems & special-purpose hardware

• 
  Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. 241-246
• 
  Avadh Patel, Kanad Ghose: Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors. 247-252
• 
  Jie Jin, Chi-Ying Tsui: A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. 253-258
• 
  Mehrdad Khatir, Amir Moradi, Alireza Ejlali, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh: A secure and low-energy logic style using charge recovery approach. 259-264
• 
  T. Venkata Kalyan, Madhu Mutyam: Word-interleaved cache: an energy efficient data cache architecture. 265-270

Low-power challenges in analog and mixed-signal front-ends

• 
  Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat: Optimal power and noise allocation for analog and digital sections of a low power radio receiver. 271-276
• 
  Xuning Chen, Gu-Yeon Wei, Li-Shiuan Peh: Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies. 277-282
• 
  Hamed Aminzadeh, Khalil Mafinezhad: On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers. 283-288
• 
  Jing-Hu Li, Yu-nan Fu, Yong-sheng Wang: A 1-V piecewise curvature-corrected CMOS bandgap reference. 289-294
• 
  Depak Balemarthy, Roy Paily: A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning. 295-300
• 
  Tahir Ghani: Innovations to extend CMOS nano-transistors to the limit. 301-302

Panel

• 
  Bodhisatya Sarker, Jaswinder Ahuja, Arijit Dutta, Srinath D., Kaip Sridhar, Radhakrishnan Nair, Jayant Lahiri: Penalty for power reduction -: performance or schedule or yield? 303-304

Industry session

• 
  Srikanth Jadcherla: SOC designs in the energy conscious era. 305-306

Tutorial

• 
  Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao: Clock gating for power optimization in ASIC design cycle theory & practice. 307-308

Run-time power & thermal management

• 
  Youngjin Cho, Younghyun Kim, Yongsoo Joo, Kyungsoo Lee, Naehyuck Chang: Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling. 309-314
• 
  Jian-Jia Chen, Lothar Thiele: Expected system energy consumption minimization in leakage-aware DVS systems. 315-320
• 
  Inchoon Yeo, Eun Jung Kim: Hybrid dynamic thermal management based on statistical characteristics of multimedia applications. 321-326
• 
  Janick Bergeron: Advances in low power verification. 327-328

System-level power estimation

• 
  Sonali Chouhan, M. Balakrishnan, Ranjan Bose: A framework for energy consumption based design space exploration for wireless sensor nodes. 329-334
• 
  Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi: Full-system chip multiprocessor power evaluations using FPGA-based emulation. 335-340
• 
  Davood Shamsi, Petros Boufounos, Farinaz Koushanfar: Noninvasive leakage power tomography of integrated circuits by compressive sensing. 341-346

Tutorials

• 
  Shashank Bhonge, Vamsi Boppana: Low power chips: a fabless asic perspective. 347-348
• 
  Wolfgang Nebel, Domenik Helms: On leakage currents: sources and reduction for transistors, gates, memories and digital systems. 349-350

Microarchitectural techniques

• 
  Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam: Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. 351-356
• 
  Gu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang: Instruction-driven clock scheduling with glitch mitigation. 357-362
• 
  José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic, Antonio González: Thread fusion. 363-368
• 
  Eric P. Villasenor, Daeho Seo, Mithuna Thottethodi: Power-efficient clustering via incomplete bypassing. 369-374
• 
  Ali Mahjur, Mahmud Taghizadeh, Amir-Hossein Jahangir: Lazy instruction scheduling: keeping performance, reducing power. 375-380
• 
  Todd M. Austin: On the rules of low-power design (and how to break them). 381-382
• 
  Takayasu Sakurai: Next-generation power-aware design. 383-384