• 
  Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino (Eds.): Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011. IEEE/ACM 2011 ISBN 978-1-61284-660-6

Keynote address

• 
  Toshihiro Hattori: Low-power and high-performance technologies for mobile SoC in LTE era. 1-2

Low voltage logic and clocking

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  Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. 3-8
• 
  Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim: Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. 9-14
• 
  Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang: Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. 15-20
• 
  Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. 21-26

Low-power design methods and tools

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  Warren Wai-Kit Shum, Jason Helge Anderson: FPGA glitch power analysis and reduction. 27-32
• 
  Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich: SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. 33-38
• 
  Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho: Pulsed-latch-based clock tree migration for dynamic power reduction. 39-44
• 
  Saro Meguerdichian, Miodrag Potkonjak: Matched public PUF: ultra low energy security platform. 45-50
• 
  Phillip Stanley-Marbell, Victoria Caparrós Cabezas, Ronald P. Luijten: Pinned to the walls: impact of packaging and application properties on the memory and power walls. 51-56

Ultra-low-voltage operation

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  Takayasu Sakurai: Designing ultra-low voltage logic. 57-58
• 
  Toshiro Hiramoto: Ultra-low-voltage operation: device perspective. 59-60
• 
  Mitsumasa Koyanagi: 3D super chip technology to achieve low-power and high-performance system-on-a chip. 61-62

Embedded tutorial

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  Manuj R. Sabharwal: Software power optimization: analysis and optimization for energy-efficient software. 63-64

Keynote address

• 
  Kee Sup Kim: Holistic low power solutions for the new world. 65-66

Low power caches

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  Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou: An energy-efficient adaptive hybrid cache. 67-72
• 
  Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh: Processor caches with multi-level spin-transfer torque ram cells. 73-78
• 
  Amin Jadidi, Mohammad Arjomand, Hamid Sarbazi-Azad: High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement. 79-84
• 
  Jongmin Lee, Seokin Hong, Soontae Kim: TLB index-based tagging for cache energy reduction. 85-90

Energy-efficient systems

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  Woojoo Lee, Younghyun Kim, Yanzhi Wang, Naehyuck Chang, Massoud Pedram, Soohee Han: Versatile high-fidelity photovoltaic module emulation system. 91-96
• 
  Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein: System energy minimization via joint optimization of the DC-DC converter and the core. 97-102
• 
  Yanzhi Wang, Younghyun Kim, Qing Xie, Naehyuck Chang, Massoud Pedram: Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systems. 103-108
• 
  David Meisner, Thomas F. Wenisch: Does low-power design imply energy efficiency for data centers? 109-114

Low power emerging technology

• 
  Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang: Analysis of power-performance for ultra-thin-body GeOI logic circuits. 115-120
• 
  Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan: Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). 121-126
• 
  Lei Jiang, Youtao Zhang, Jun Yang: Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling. 127-132

Reliability and thermal issues

• 
  Chin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li: TG-based technique for NBTI degradation and leakage optimization. 133-138
• 
  Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang: Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. 139-144
• 
  Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester: Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs. 145-150
• 
  Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza: Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs. 151-156

Poster session

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  David Li, Pierce Chuang, David Nairn, Manoj Sachdev: Design and analysis of metastable-hardened flip-flops in sub-threshold region. 157-162
• 
  Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. 163-168
• 
  Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang: 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. 169-174
• 
  Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Reduction of minimum operating voltage (V_DDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection. 175-180
• 
  Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer: Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. 181-186
• 
  Amir Zjajo, José Pineda de Gyvez: A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. 187-192
• 
  Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu: A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique. 193-198
• 
  Jong-Kwan Woo, Tae-Hoon Kim, Hyongmin Lee, Sunkwon Kim, Hyunjoong Lee, Suhwan Kim: A comparator-based cyclic analog-to-digital converter with boosted preset voltage. 199-204
• 
  Po-Hsun Wu, Tsung-Yi Ho: Thermal-aware bus-driven floorplanning. 205-210
• 
  Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem: An approach to energy-error tradeoffs in approximate ripple carry adders. 211-216
• 
  Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. 217-222
• 
  Ce Li, Yiping Dong, Takahiro Watanabe: New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM. 223-228
• 
  Azalia Mirhoseini, Farinaz Koushanfar: Learning to manage combined energy supply systems. 229-234
• 
  Sehwan Kim, Pai H. Chou: Energy harvesting by sweeping voltage-escalated charging of a reconfigurable supercapacitor array. 235-240
• 
  Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura: On-chip detection methodology for break-even time of power gated function units. 241-246
• 
  Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta: Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. 247-252
• 
  Youngtaek Kim, Lizy Kurian John: Automated di/dt stressmark generation for microprocessor power delivery networks. 253-258
• 
  Denis Dondi, Piero Zappi, Tajana Simunic Rosing: A scheduling algorithm for consistent monitoring results with solar powered high-performance wireless embedded systems. 259-264
• 
  Aaron Carpenter, Jianyun Hu, Michael C. Huang, Hui Wu, Peng Liu: A design space exploration of transmission-line links for on-chip interconnect. 265-270
• 
  Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada: An integrated optimization framework for reducing the energy consumption of embedded real-time applications. 271-276
• 
  Karthik Kumar, Kshitij A. Doshi, Martin Dimitrov, Yung-Hsiang Lu: Memory energy management for an enterprise decision support system. 277-282

Keynote address

• 
  Sachin S. Sapatnekar: The whys and hows of thermal management. 283-284

SRAM

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  Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii: A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. 285-290
• 
  Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang: A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. 291-296
• 
  Joseph F. Ryan, Sudhanshu Khanna, Benton H. Calhoun: An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal. 297-302
• 
  Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy: Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. 303-308

Software based techniques for energy optimization

• 
  Pi-Cheng Hsiu, Chun-Han Lin, Cheng-Kang Hsieh: Dynamic backlight scaling optimization for mobile streaming applications. 309-314
• 
  Aldhino Anggorosesar, Young-Jin Kim: Object-based local dimming for LCD systems with LED BLUs. 315-320
• 
  Raid Zuhair Ayoub, Ümit Y. Ogras, Eugene Gorbatov, Yanqin Jin, Timothy Kam, Paul Diefenbaugh, Tajana Rosing: OS-level power minimization under tight performance constraints in general purpose systems. 321-326
• 
  Xin Fan, Shigeru Kusakabe: Energy efficient scheduling for multithreaded programs on general-purpose processors. 327-332
• 
  Carlo Brandolese, Simone Corbetta, William Fornaciari: Software energy estimation based on statistical characterization of intermediate compilation code. 333-338
• 
  Mahsan Rofouei, Miodrag Potkonjak, Majid Sarrafzadeh: Energy efficient E-textile based portable keyboard. 339-344

Keynote address

• 
  Yasunori Miyahara: Next-generation wireless technologies trends for ultra low energy. 345-346

Innovations in low-power analog

• 
  Sunkwon Kim, Jong-Kwan Woo, Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Hyunjoong Lee, Suhwan Kim: A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications. 347-350
• 
  Liyuan Liu, Dongmei Li, Yafei Ye, Zhihua Wang: A 92.4dB SNDR 24kHz ΔΕ modulator consuming 352μW. 351-356
• 
  Hyunjoong Lee, Hyongmin Lee, Jong-Kwan Woo, Sunkwon Kim, Young June Park, Suhwan Kim: A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system. 357-360
• 
  György D. Szarka, Plamen P. Proynov, Bernard H. Stark, Stephen G. Burrow, Neville McNeill: Experimental investigation of inductorless, single-stage boost rectification for sub-mW electromagnetic energy harvesters. 361-366

Green HPC

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  Satoshi Matsuoka: Making TSUBAME2.0, the world's greenest production supercomputer, even greener: challenges to the architects. 367-368
• 
  Ken Takeuchi: Green high performance storage class memory & NAND flash memory hybrid SSD system. 369-370
• 
  Mitsuo Yokokawa, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa, Tadashi Watanabe: The K computer: Japanese next-generation supercomputer development project. 371-372

Low power micro-architecture

• 
  Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto: A 98 GMACs/W 32-core vector processor in 65nm CMOS. 373-378
• 
  Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González: Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. 379-384
• 
  Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava: Fast and energy-efficient constant-coefficient FIR filters using residue number system. 385-390
• 
  Junyoung Park, Jacob A. Abraham: A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems. 391-396

Power issues in interconnect and domain-specific architecture

• 
  Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie: Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs. 397-402
• 
  Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar: NoC frequency scaling with flexible-pipeline routers. 403-408
• 
  Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy: IMPACT: imprecise adders for low-power approximate computing. 409-414