Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 1990. IEEE Computer Society Press, 1990, ISBN 0-8186-2046-3

Keynote Address

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  C. M. Allen: Multi-Valued Logic: Wave of the Future or an Historical Anachronism. 1

Circuits

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  Jonathan Wayne Mills, M. Gordon Beavers, Charles A. Daffinger: Lukasiewicz Logic Arrays. 4-10
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  Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto: On Design of Multiple-Valued Static Random-Access-Memory. 11-17
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  Takahiro Hanyu, Tatsuo Higuchi: Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. 18-23
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  J. M. Johnson: Ternary Logic Elements for Self-timed Integrated Systems. 24
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  Orlando E. Katter Jr., Hassan M. Razavi: A New CMOS Gate - The Balanced Gate - For Detecting Physical Failures. 25-31

Algebra I

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  Lucien Haddad, Ivo G. Rosenberg: A Note on Finite Clones Containing All Permutations. 34-41
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  George Epstein, Helena Rasiowa: Theory and Uses of Post Algebras of Order omega+omegaw\ast.I. 42-47
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  Corina Reischer, Dan A. Simovici: Bio-Algebras. 48-53
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  Louis H. Kaufman: Robbins Algebra. 54-60

Spectral Techniques

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  Claudio Moraga, Jörg Poswig: Properties of the Zhang-Hartley Spectrum of Patterns. 62-68
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  T. Raju Damarla: Fault Detection in Multiple Valued Logic Circuits. 69-74
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  Bogdan J. Falkowski, Marek A. Perkowski: Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions. 75-82

Algebra II

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  Aldo V. Figallo, Luiz Monteiro, Alicia Ziliani: Free Three-valued Lukasiewicz, Post and Moisil Algebras over a Poset. 433-435
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  Josep Maria Font, Miquel Rius: A Four-Valued Modal Logic Arising from Monteiro's Last Algebras. 85-92
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  Noboru Takagi, Masao Mukaidono: Kleene-Stone Logic Functions. 93-100

Special Applications I

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  Deepak Dube, Anneliese von Mayrhauser: Alleviating Memory Bottlenecks Using Multi-Level Memory. 102-109
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  Oscar N. Garcia, Massoud Moussavi: A Six-Valued Logic for Representing Incomplete Knowledge. 110-114
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  A. Sengupta, C. Rhee: On the Diagnosability of Systems with Three Valued Test Results: Diagnosis by Comparison Strategy. 115-120
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  Jia-Yuan Han, Supreet Singh: Comparison Look-Ahead and Design of Fast Fuzzy Operation Units. 121-125

Logic Design I

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  Tsutomu Sasao: EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. 128-135
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  Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. 136-143
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  John M. Yurchak, Jon T. Butler: HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. 144-152
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  Chyan Yang, Yao-Ming Wang: A Neighborhood Decoupling Algorithm for Truncated Sum Minimization. 153-160

Invited Address

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  Michitaka Kameyama: Toward the Age of Beyond-Binary Electronics and Systems. 162-166

Circuits II

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  K. Wayne Current: A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. 168-173
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  Debashis Bhattacharya: Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. 174-180
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  Peter Baltus, Pieter van der Meulen, Ross Morley: An Efficient Multi-Level Multi-Wire Differential Interface. 181-188
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  Lutz J. Micheel, Michael J. Paulus: Differential Multiple-Valued Logic Using Resonant Tunneling Diodes. 189-195
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  Mou Hu, Kenneth C. Smith: Application of Multiple-Valued Switch-Level Algebra to the Design and Analysis of Pass-Transistor Switch Networks. 196-201

Logic

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  Zbigniew Stachniak: Note on Resolution Approximation of Many-Valued Logics. 204-209
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  I. R. Goodman: Conditional Event Algebras and Logic, Part I: Motivation and History of the Problem. 210
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  Michael F. Schmidt: On Some Neglected Paradoxes of Modem Logic. 211-219
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  Nuno J. Mamede, João P. Martins: Bringing Resources into Logic. 220-227
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  Kazimierz Trzesicki: Many-Valued Tense Logic and the Problem of Determinism. 228-236

Invited Address

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  Melvin Fitting: Bilattices in Logic Prograrnming. 238-246

Logic and Algebra

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  János Demetrovics, Masahiro Miyakawa, Ivo G. Rosenberg, Dan A. Simovici, Ivan Stojmenovic: Intersections of Isotone Clones on a Finite Set. 248-253
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  Masahiro Miyakawa, Ivan Stojmenovic, Dietlinde Lau, Taketoshi Mishima: On the Structure of Maximal Closed Sets of P_K2. 254-261
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  Hantao Zhang: Approximate Reasoning in Strength Logic. 262-269
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  O. O. Silva, C. R. Souza: Induction of Fuzzy Production Rules. 270-278
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  Lichun Cheng, Mou Hu: A General Fuzzy Logical Operator Set. 279-283

Logic Design II

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  Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer: A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. 286-291
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  Jon C. Muzio: Concerning the Maximum Size of the Terms in the Realization of Symmetric Functions. 292-299
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  Safwat G. Zaky, Zvonko G. Vranesic, Mostafa H. Abd-El-Barr: Step-Wise Synthesis of CCD MVL Functions. 300-307
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  Srinivas Devadas: Minimization of Functions with Multiple-Valued Outputs: Theory and Applications. 308-315
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  Mostafa H. Abd-El-Barr, H. Choy: On the Synthesis of MVMT Functions for PLA Implementation Using CCDs. 316-323

Invited Address

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  Ryszard S. Michalski: Theory of Plausible Reasoning - Foundations and Methodology. 325

Logic and Artificial Intelligence

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  Walter Alexandre Carnielli: Many-Valued Logics and Plausible Reasoning. 328-335
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  Masamitu Otake, Taketoshi Mishima, Yoichi Manome: Strength of the Rule of Inference. 336-338
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  V. S. Subrahmanian: Paraconsistent Disjunctive Deductive Databases. 339-346

Circuits III

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  Daniel Etiemble, C. Chanussot, Vincent Néri: 4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture. 348-354
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  Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi: Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. 355-362
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  Hsu Liang Ho, Kenneth C. Smith: Integrator-Chain Multiplier. 363-369

Artificial Intelligence and Expert Systems

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  Zbigniew W. Ras: Fault-Recovery and Intelligent Distributed System. 372-377
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  W. Elliott Jr., M. Schneider: The Learning Aspects of the Fault Finder Expert System. 378-385
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  Rudolf Felix: Goal-Oriented Control of VLSI Design Processes Based on Fuzzy Sets. 386-393
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  Zhijian Li, Hong Jiang: A CMOS Current-Mode High Speed Fuzzy Logic Microprocessor for a Real-Time Expert System. 394-401

Special Applications II

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  Kevin Cattell, Micaela Serra: The Analysis of One Dimensional Multiple-Valued Linear Cellular Automata. 402-409
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  Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato: Some Relationships Between Multiple-Valued Kleenean Functions and Ternary Input Multiple-Valued Output Functions. 410-417
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  Tatsuki Watanabe, Masayuki Matsumoto, Mitsuaki Enokida, Takahiro Hasegawa: A Design of Multiple-Valued Logic Neuron. 418-425
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  Loke-Soo Hsu, Hoon heng Teh, Sing-Chai Chan, Kia-Fock Loe: Multi-Valued Neural Logic Networks. 426-432