21. ISMVL 1991: Victoria, BC, Canada

Invited Address

• Anthony S. Wojcik: Reasoning About Digital Systems. 2-6

Applications I

• Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi: Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. 8-15
• Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi: A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. 16-23
• Takahiro Hanyu, Tatsuo Higuchi: A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. 24-31
• Chia-Lun J. Hu: Application of Multi-Zero Artificial Neural Network to the Design of an M-Valued Digital Multiplier. 32-37

Logic

• Ingo Schäfer, Marek A. Perkowski: Multiple-Valued Generalized Reed-Muller Forms. 40-48
• Robert J. Bignall: A Non-Commutative Multiple-Valued Logic. 49-54
• Yutaka Hata, Masaharu Yuhara, Fujio Miyawaki, Kazuharu Yamato: On the Complexity of Enumerations for Multiple-Valued Kleenean Functions and Unate Functions. 55-62
• Noboru Takagi, Masao Mukaidono: Fundamental Properties of Kleene-Stone Logic Functions. 63-70

Fuzzy Logic

• Lluis Godo, Francesc Esteva, Pere Garcia, Jaume Agustí-Cullell: A Formal Semantical Approach to Fuzzy Logic. 72-79
• Akira Nakamura: Topological Soft Algebra for the S5-Modal Fuzzy Logic. 80-84
• Tatsuki Watanabe, Masayuki Matsumoto: Recognition of Circle Form Using Fuzzy Sequential System. 85-92

Symmetric Functions/Error Correction

• Jon T. Butler, Kriss A. Schueller: Worst Case Number of Terms in Symmetric Multiple-Valued Functions. 94-101
• Yoshiteru Okura, Ryosaku Shimada, Toshiharu Hasegawa: Quaternary Cyclic AN Codes for Burst Error Correction. 102-109
• Ratko Tosic, Ivan Stojmenovic, Masahiro Miyakawa: On the Maximum Size of the Terms in the Realization of Symmetric Functions. 110-117

Invited Address

• Hiroyuki Watanabe, James R. Symon, Wayne D. Dettloff, Kathy E. Yount: VLSI Fuzzy Chip and Inference Accelerator Board Systems. 120-127

Cost Tables

• Young-hoon Chang, Jon T. Butler: The Design of Current Mode CMOS Multiple-Valued Circuits. 130-138
• Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto: Synthesis of Current-Mode Pass Transistor Networks. 139-146
• Konrad Lei, Zvonko G. Vranesic: On the Synthesis of 4-Valued Current Mode CMOS Circuits. 147-155

Testability/Bio-Computing

• Come Rozon, H. T. Mouftah: Testability Analysis of CMOS Temary Circuits. 158-165
• Corina Reischer, Dan A. Simovici: On the Implementation of Set-Valued Non-Boolean Switching Functions. 166-172
• Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi: Design of Interconnection-Free Biomolecular Computing System. 173-180

Invited Address

• Claudio Moraga: A Decade of Spectral Techniques. 182-188

Circuits

• Sen Jung Wei, Hung Chang Lin: Multiple Peak Resonant Tunneling Diode for Multi-Valued Memory. 190-195
• K. Wayne Current, M. E. Hurlston: A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. 196-202
• Babak A. Taheri: Proposed CMOS VLSI Implementation of an Electronic Neuron Using Multivalued Signal Processing. 203-209
• Xunwei Wu, Xiaowei Deng: Theory of Grounded Current Switches and Quatemary IIL Circuits. 210-215

Reasoning

• Eric Neufeld: The Abnormality Predicate. 218-224
• Frank J. Wroblewski: Undecidability in the Completion of Truth-Function Logic. 225-229
• Neil V. Murray, Erik Rosenthal: Improving Tableau Deductions in Multiple-Valued Logics. 230-237
• Reiner Hähnle: Uniform Notation of Tableau Rules for Multiple-Valued Logics. 238-245

Algebra

• George Epstein, Helena Rasiowa: Theory and Uses of Post Algebras of Order \omega+\omega\ast. Part II. 248-254
• Wen-Ran Zhang: NPN Calculi: A Family of Three Strict Q-Algebras. 255-261
• Ferdinand Börner, Lucien Haddad, Reinhard Pöschel: A Note on Minimal Partial Clones. 262-267

Function Minimization

• Tsutomu Sasao: A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions. 270-279
• Gerhard W. Dueck, G. H. John van Rees: On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. 280-286
• Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry: Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. 287-295

Invited Address

• Ewa Orlowska: Post Relation Algebras and Their Proof System. 298-305

Expert Systems

• David C. Rine: An Equational Logic Approach for Mapping Multiple-Valued Rule-Based Expert Systems into Hardware Specification Rules. 308-315
• Caro Lucas, I. Burhan Türksen, Kenneth C. Smith: A General-Purpose Inference Processor for Real-Time Intelligent Controllers Using Systolic Arrays. 316-321
• Yoshifumi Tsuchiya: An Algorithm for the Solution of Multi-Valued Logic Programming. 322-327

Spectral Techniques/Number Systems

• Shoji Kawahito, K. Mizuno, Tasuro Nakamura: Multiple-Valued Current-Mode Arithmetic Circuits Based on Redundant Positive-Digit Number Representations. 330-339
• T. Raju Damarla, Fiaz Hossain: Spectral Techniques for Multiple-Valued Logic Circuits. 340-346

Fuzzy Logic Hardware

• Tzi-cker Chiueh: Optimization of Fuzzy Logic Implementation. 348-355
• Mamoru Sasaki, Fumio Ueno: A Fuzzy Logic Function Generator (FLUG) Implemented with Current Mode CMOS Circuits. 356-362

Programmable Logic

• Chyan Yang, Han-Chung Lu, David E. Gilbert: An Investigation into the Implementation Costs of Residue and High Radix Arithmetic. 364-371
• Mostafa H. Abd-El-Barr, H. Choy, A. K. Jain, R. J. Bolton: A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions. 372-381

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