22nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 1992), May 27-29, 1992, Sendai, Japan, Proceedings. IEEE Computer Society, 1992, ISBN 0-8186-2680-1

Session 1: Invited Address

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  Shinya Hasuo: High-Speed Digital Circuits for a Josephson Computer. 2-8

Session 2A: Device-Based Circuit

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  Mititada Morisue, Fu-Qiang Li: A Superconducting Ternary Systolic Array Processor. 10-17
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  Lutz J. Micheel: Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and Multipliers. 18-26
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  Sen Jung Wei, Hung Chang Lin: Unique Folding and Hysteresis Characteristics of RTD for Multi-Valued Logic and Counting Applications. 27-33

Session 2B: Test

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  Naotake Kamiura, Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato: Easily Testable Multiple-Valued Cellular Arrays. 36-42
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  Geetani Edirisooriya, John P. Robinson: Aliasing in Multiple-Valued Test Data Compaction. 43-50
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  Hassan M. Razavi, Paul W. Wong: A New Balanced Gate for Structural Testing. 51-55

Session 3A: Logic Minimization

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  Gerhard W. Dueck: Direct Cover MVL Minimization with Cost-Tables. 58-65
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  Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. 66-74
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  Chyan Yang, Onur Oral: Experiences of Parallel Processing with Direct Cover Algorithms for Multiple-Valued Logic Minimization. 75-82

Session 3B: Neural Network

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  Chia-Lun J. Hu: Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous Two-Layered Neural Network. 84-87
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  Tatsuki Watanabe, Masayuki Matsumoto: Layered MVL Neural Networks Capable of Recognizing Translated Characters. 88-95
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  Joo-Hwee Lim, Ho-Chung Lui, Hoon heng Teh: A Deductive Neural-Logic System. 96-102

Session 4A: Circuit Design

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  Konrad Lei, Zvonko G. Vranesic: Towards the Realization of 4-Valued CMOS Circuits. 104-110
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  Mostafa H. Abd-El-Barr, H. Choy: Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions. 111-118
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  Xunwei Wu: The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits. 119-125

Session 4B: Algebra 1

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  Takahiro Haga: An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the p-Valued Logical Networks. 128-137
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  Kiyomichi Araki, Masayuki Takada, Masakatu Morii: On the Efficient Decoding of Reed-Solomon Codes Based on GMD Criterion. 138-145
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  Patrick Doherty, Witold Lukaszewicz: Defaults as First-Class Citizens. 146-154

Session 5: Invited Address

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  Daniel Etiemble: On the Performance of Multivalued Integrated Circuits: Past, Present and Future. 156-164

Session 6A: Reliable Systems

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  David Wessels, Jon C. Muzio: Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits. 166-173
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  Masayoshi Sakai, Masakazu Kato, Koichi Futsuhara, Masao Mukaidono: Application of Fail-Safe Multiple-Valued Logic to Control of Power Press. 174-180
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  Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. 181-188

Session 6B: Algebra 2

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  M. C. Canals Frau, Aldo V. Figallo: (n+1)-Valued Modal Implicative Semilattices. 190-196
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  Jizhong Shen: Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I). 198-205

Session 7A: Current Mode Circuits

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  Edward K. F. Lee, P. Glenn Gulak: Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction. 208-215
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  Kazutaka Taniguchi, Mamoru Sasaki, Yutaka Ogata, Fumio Ueno, Takahiro Inoue: Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply Voltage. 216-220
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  Mostafa H. Abd-El-Barr, M. I. Mahroos: On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation. 221-228
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  K. Wayne Current: A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. 229-234

Session 7B: Algebra 3

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  Kyoichi Nakashima, Noboru Takagi: On Multiple-Valued Logic Functions Monotonic with Respect to Ambiguity. 236-242
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  Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono: Fundamental Properties of Extended Kleene-Stone Logic Functions. 243-249
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  Ratko Tosic, Ivan Stojmenovic, Dan A. Simovici, Corina Reischer: On Set-Valued Functions and Boolean Collections. 250-254
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  Reinhard Pöschel, M. Reichel: Rectangular Algebras. 255-260

Session 8: Invited Address

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  Marek A. Perkowski: A Universal Logic Machine. 262-271

Session 9A: VLSI 1

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  Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi: Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. 274-281
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  Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi: Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. 282-290
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  Jonathan Wayne Mills: Area-Efficient Implication Circuits for Very Dense Lukasiewicz Logic Arrays. 291-298

Session 9B: Completeness

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  Masahiro Miyakawa, Akihiro Nozaki, Grant Pogosyan, Ivo G. Rosenberg: Semigrid Sets of Central Relations Over a Finite Domain. 300-307
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  V. Lashkia: Amplification of the Functional Closure Operation. 308-311

Session 10: Invited Address

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  Ágnes Szendrei: A Completeness Criterion for Semi-Affine Algebras. 314-319

Session 11A: VLSI 2

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  Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi: Design of a Multiple-Valued VLSI Processor for Digital Control. 322-329
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  Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi: Residue Arithmetic Based Multiple-Valued VLSI Image Processor. 330-336
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  Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura: Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. 337-345

Session 11B: Spectral Techniques

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  Philipp W. Besslich, E. A. Trachtenberg: Binary Input/Ternary Output Switching Circuits Designed Via the Sign Transformation. 348-354
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  R. Tomczuk, D. Michael Miller: Autocorrelation Techniques for Multi-Bit Decoder PLAs. 355-364
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  Radomir S. Stankovic: Some Remarks on Fourier Transform and Differential Operators for Digital Functions. 365-370

Session 12: Special Session

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  Susan W. Butler, Jon T. Butler: Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. 372-379

Session 13A: Logic Design

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  Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi: Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. 382-388
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  Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato: Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions. 389-395
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  Mou Hu, Shensheng Xu, Kenneth C. Smith: On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary MOS Bridge Circuits and Dynamic Circuits. 396-400
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  Benchu Fei, Nan Zhuang: Fast Logic Synthesis Based Upon Ternary Universal Logic Module _f. 401-407

Session 13B: Fuzzy Logic 1

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  Fumio Ueno, Takahiro Inoue, Badur-ul-Haque Baloch, Takayoshi Yamamoto: An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy Inference. 410-414
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  Yoshinori Yamamoto: A Meaningful Infinite-Valued Switching Function - Fuzzy Threshold Function and Its Application to Process Control. 415-422
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  Yuji Shirai, Fumio Ueno, Takahiro Inoue, Motohiro Inoue, Kouji Tasaki: Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode Fuzzy State Memory. 423-427
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  Hiroshi Ito, Takashi Matsubara, Takakazu Kurokawa, Yoshiaki Koga: A Proposal of Fault-Checking Fuzzy Control. 428-434

Session 14A: EXOR Logic

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  Berthold Harking, Claudio Moraga: Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems. 436-441
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  Marek A. Perkowski: The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications. 442-450
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  Tsutomu Sasao: Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. 451-458

Session 14B: Fuzzy Logic 2

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  Akira Nakamura: On a Logic Based on Fuzzy Modalities. 460-466
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  Zuliang Shen, Liya Ding, Ho-Chung Lui, Pei-Zhuang Wang, Masao Mukaidono: Revision Principle for Approximate Reasoning-Based on Semantic Revising Method. 467-473
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  Heinz J. Skala: On Yager's Aggregation Operators. 474-477

Session 15: Invited Address

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  Lotfi A. Zadeh: Fuzzy Logic and the Calculus of Fuzzy If-Then Rules. 480