27. ISMVL 1997: Antigonish, Nova Scotia, Canada

Invited Address

• D. Rooß:
  Recent Developments in DNA-Computing. 3-
  

Decomposition I

• Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang:
  Decomposition of Multiple-Valued Relations . 13-18
  
• Elena Dubrova, Jon C. Muzio, Bernhard von Stengel:
  Finding Composition Trees for Multiple-Valued Functions. 19-26
  
• Craig M. Files, Rolf Drechsler, Marek A. Perkowski:
  Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. 27-
  

Technology

• Takao Waho, Masafumi Yamamoto:
  Application of Resonant-Tunneling Quaternary Quantizer to Ultrahigh-Speed A/D Converter. 35-40
  
• Toshio Baba, Tetsuya Uemura:
  Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits . 41-46
  
• Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi:
  Enzyme Transistor Circuits for Biomolecular Computing. 47-
  

Minimization I

• Tsutomu Sasao, Jon T. Butler:
  Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. 55-60
  
• Arkadij Zakrevskij, Lev Zakrevski:
  Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions. 61-65
  
• Rolf Drechsler, Martin Keim, Bernd Becker:
  Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. 66-
  

Algebra

• Alioune Ngom, Corina Reischer, Dan A. Simovici, Ivan Stojmenovic:
  Completeness Criteria in Set-Valued Logic Under Compositions with Union and Intersection. 75-82
  
• Boris A. Romov:
  Hyperclones on a Finite Set. 83-88
  
• Noboru Takagi, Y. Nakamura, Kyoichi Nakashima:
  Set-Valued Functions and Regularity. 89-
  

Minimization II

• Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato:
  Multiple-Valued Logic Minimization by Genetic Algorithms. 97-102
  
• Yutaka Hata, Naotake Kamiura, Kazuharu Yamato:
  Multiple-Valued Product-of-Sums Expression with Truncated Sum. 103-
  

Philosophical Aspects

• Phan Hong Giang:
  Representation of Uncertain Belief Using Interval Probability. 111-116
  
• Jean-Yves Béziau:
  What Is Many-Valued Logic? 117-
  

Spectral Techniques

• Susanto Rahardja, Bogdan J. Falkowski:
  Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra. 125-130
  
• Bogdan J. Falkowski, Susanto Rahardja:
  Properties and Applications of Unified Complex Hadamard Transforms. 131-
  

Testing and Fault Simulation

• Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko:
  Test Pattern Generation for Combinatorial Multi-Valued Networks Based on Generalized D-Algorithm. 139-144
  
• Rolf Drechsler, Martin Keim, Bernd Becker:
  Fault Simulation in Sequential Multi-Valued Logic Networks. 145-
  

Invited Address

• Ewa Orlowska:
  Many-Valuedness and Uncertainty. 153-
  

Circuit Applications

• T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
  Multiple-Valued Programmable Logic Arrays with Universal Literals. 163-168
  
• Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko:
  VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. 169-174
  
• Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
  One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. 175-
  

Fuzzy Logic

• Helmut Thiele:
  On the Mutual Definability of Classes of Generalized Fuzzy Implications and of Classes of Generalized NegationsandS-Norms. 183-188
  
• Junda Chen, David C. Rine:
  Training Fuzzy Logic Based Software Components for Reuse. 189-194
  
• Erdmuthe Meyer zu Bexten, F. Sajadi, Claudio Moraga:
  Properties of Lindenmayer Fuzzy Languages and a-Driven Lindenmayer Languages. 195-
  

Circuits

• Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni:
  Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. 203-208
  
• Xunwei Wu, Massoud Pedram:
  Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits. 209-214
  
• Andreas Herrfeld, Siegbert Hentschke:
  Quatemary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits. 215-
  

Applications

• Seiki Akama:
  A Proof Method for the Six-Valued Logic for Incomplete Information. 223-226
  
• Robert J. Bignall, Matthew Spinks:
  Multiple-Valued Logic as a Programming Language. 227-232
  
• Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno:
  Multiple-Valued Immune Network Model and Its Simulations. 233-
  

Invited Address

• Tsutomu Sasao:
  Ternary Decision Diagrams: Survey. 241-
  

Logic Design

• Mostafa H. Abd-El-Barr, M. N. Hasan, G. A. Hamid:
  On the Synthesis of MVL Functions Using Input and Output Phase Assignments. 253-258
  
• A. Etzel:
  Mixed Discrete Optimization of Multiple-Valued Systems. 259-264
  
• Yasunori Nagata, Masao Mukaidono:
  Design of an Asynchronous Digital System with B-Ternary Logic. 265-
  

Function Representation

• Radomir S. Stankovic, Rolf Drechsler:
  Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. 275-280
  
• Radomir S. Stankovic:
  Fourier Decision Diagrams on Finite Non-Abelian Groups with Preprocessing. 281-286
  
• Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak:
  Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. 287-292
  

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