ISPAN 2000:
Dallas / Richardson, TX, USA
5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA.
IEEE Computer Society 2000, ISBN 0-7695-0936-3
Parallel Algorithms
Routing and Communications
Networks 1
Architecture 1
Fault Tolerance
Scheduling
Networks 2
Telecommunications
Routing
- Ioannis Caragiannis, Christos Kaklamanis, Ioannis Vergados:
Greedy Dynamic Hot-Potato Routing on Arrays.
178-185

- Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
186-194

- Carmen Carrión, José A. Gregorio, Ramón Beivide:
Pipelining Router Design Improves Parallel System Performance.
195-201

Networks 3
Parallel Algorithms
Ad-Hoc Networks
Architecture 2
Broadcasting
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