ISPASS 2004: Austin, Texas, USA

• Yale N. Patt:
  Opening and keynote 1. 1
  
• Hans Vandierendonck, Koen De Bosschere:
  Eccentric and fragile benchmarks. 2-11
  
• Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin:
  Communication breakdown: analyzing CPU usage in commercial Web workloads. 12-19
  
• Erik Berg, Erik Hagersten:
  StatCache: a probabilistic approach to efficient and accurate data locality analysis. 20-27
  
• Pavan Balaji, Sundeep Narravula, Karthikeyan Vaidyanathan, Savitha Krishnamoorthy, Jiesheng Wu, Dhabaleswar K. Panda:
  Sockets Direct Protocol over InfiniBand in clusters: is it beneficial? 28-35
  
• Leonardo R. Bachega, José R. Brunheroto, L. DeRose, Pedro Mindlin, José E. Moreira:
  The BlueGene/L pseudo cycle-accurate simulator. 36-44
  
• Michael Van Biesbrouck, Timothy Sherwood, Brad Calder:
  A co-phase matrix to guide simultaneous multithreading simulation. 45-56
  
• Jeremy Lau, Stefan Schoenmackers, Brad Calder:
  Structures for phase classification. 57-67
  
• Gordon B. Bell, Mikko H. Lipasti:
  Deconstructing commit. 68-77
  
• Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho, Michael C. Huang:
  Dynamically reducing pressure on the physical register file through simple register sharing. 78-87
  
• Ying Zheng, Brian T. Davis, Matthew Jordan:
  Performance evaluation of exclusive cache hierarchies. 89-96
  
• C. Anderson:
  Keynote II. 97
  
• Irina Chihaia, Thomas R. Gross:
  Effectiveness of simple memory models for performance prediction. 98-105
  
• Rong Xu, Zhiyuan Li:
  Using cache mapping to improve memory performance handheld devices. 106-114
  
• R. Bonilla-Lucas, Peter Plachta, Aamer Sachedina, Daniel Jiménez-González, Calisto Zuzarte, Josep-Lluis Larriba-Pey:
  Characterization of the data access behavior for TPC-C traces. 115-122
  
• Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge:
  Cache implications of aggressively pipelined high performance microprocessors. 123-132
  
• Wei Huang, Witawas Srisa-an, J. Morris Chang:
  Dynamic pretenuring schemes for generational garbage collection. 133-140
  
• Mikhail Dmitriev:
  Selective profiling of Java applications using dynamic bytecode instrumentation. 141-150
  
• Russ Joseph, Margaret Martonosi, Zhigang Hu:
  Spectral analysis for characterizing program power and performance. 151-160
  
• Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam:
  Compiler-directed physical address generation for reducing dTLB power. 161-168
  
• Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith:
  The future of simulation: A field of dreams. 169
  
• Lieven Eeckhout:
  Efficient architectural design of high performance microprocessors. 170
  
• W. Wolf:
  Architectures and compilers for multimedia. 171