ISPASS 2005: Austin, Texas, USA

Keynote

• Markus Levy:
  EEMBC and the Purposes of Embedded Processor Benchmarking. 1
  

Benchmarking

• Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung:
  BioBench: A Benchmark Suite of Bioinformatics Applications. 2-9
  
• Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, Lizy Kurian John:
  Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites. 10-20
  
• Gabriel H. Loh:
  Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. 21-31
  

Power and thermal management

• Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge:
  PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. 32-41
  
• YongKang Zhu, David H. Albonesi, Alper Buyuktosunoglu:
  A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. 42-53
  
• Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke:
  Studying Thermal Management for Graphics-Processor Architectures. 54-65
  

Accelerating Simulation

• Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovic:
  Accelerating Multiprocessor Simulation with a Memory Timestamp Record. 66-77
  
• Jeff Ringenberg, Chris Pelosi, David W. Oehmke, Trevor N. Mudge:
  Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification. 78-88
  
• Magnus Ekman, Per Stenström:
  Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. 89-99
  

Panel

• Erik R. Altman:
  Panel Discussion: Architectures for the Future. 100
  

Keynote

• Thomas M. Conte:
  Insight, not (random) numbers. 101
  

Multithreading

• Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang:
  Performance Characterization of Java Applications on SMT Processors. 102-111
  
• Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas:
  Partitioning Multi-Threaded Processors with a Large Number of Threads. 112-123
  
• Jian Li, José F. Martínez:
  Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors. 124-134
  

Statistical and trace-driven simulation

• Jeremy Lau, Erez Perelman, Greg Hamerly, Timothy Sherwood, Brad Calder:
  Motivation for Variable Length Intervals and Hierarchical Phase Behavior. 135-146
  
• Ram Srinivasan, Jeanine Cook, Shaun Cooper:
  Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection. 147-156
  
• Hyrum Carroll, J. Kelly Flanagan, Satish Baniya:
  A Trace-Driven Simulator For Palm OS Devices. 157-166
  

Data parallel processing

• Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero:
  On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. 167-176
  
• Mihai Budiu, Pedro V. Artigas, Seth Copen Goldstein:
  Dataflow: A Complement to Superscalar. 177-186
  
• Yuan Zhao, Ken Kennedy:
  Scalarization on Short Vector Machines. 187-196
  

Network processing

• Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan:
  Anatomy and Performance of SSL Processing. 197-206
  
• Annie Foong, Jason Fung, Donald Newell, Seth Abraham, Peggy Irelan, Alex Lopez-Estrada:
  Architectural Characterization of Processor Affinity in Network Processing. 207-218
  
• Raimir Holanda, Javier Verdú, Jorge García-Vidal, Mateo Valero:
  Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering. 219-225
  

Performance and workload characterization

• Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf:
  Analysis of Network Processing Workloads. 226-235
  
• Jeremy Lau, Jack Sampson, Erez Perelman, Greg Hamerly, Brad Calder:
  The Strong correlation Between Code Signatures and Performance. 236-247
  
• Murali Vilayannur, Anand Sivasubramaniam, Mahmut T. Kandemir:
  Pro-active Page Replacement for Scientific Applications: A Characterization. 248-257
  

Communication and reliability

• Kevin M. Lepak, Mikko H. Lipasti:
  Reaping the Benefit of Temporal Silence to Improve Communication Performance. 258-268
  
• Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli:
  Balancing Performance and Reliability in the Memory Hierarchy. 269-279
  
• Pavan Balaji, Sundeep Narravula, Karthikeyan Vaidyanathan, Hyun-Wook Jin, Dhabaleswar K. Panda:
  On the provision of prioritization and soft qos in dynamically reconfigurable shared data-centers over infiniband. 280-289
  

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